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publication number s25fl032p_00 revision 09 issue date january 29, 2013 s25fl032p s25fl032p cover sheet 32-mbit cmos 3.0 volt flash memory with 104-mhz spi (serial peripher al interface) multi i/o bus data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informat ion or preliminary designati ons to advise readers of product information or intended s pecifications throughout the produc t life cycle, including development, qualification, initial production, and full production. in all cases, however, reader s are encouraged to verify that they have the latest information before finalizi ng their design. the following descriptions of spansion data sheet designations are presented here to hi ghlight their presenc e and definitions. advance information the advance information designation i ndicates that spansion inc. is de veloping one or more specific products, but has not committed any des ign to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore plac es the following conditions upo n advance information content: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has pr ogressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under c onsideration. spansion places the following conditi ons upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designati ons (advance information, preliminary, or full production). th is type of document distinguishes t hese products and their designations wherever necessary, typically on the first page, th e ordering information page, and pages with the dc characteristics table and the ac er ase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of ti me such that no changes or only nominal changes are expected, the preliminary desi gnation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the a ddition or deletion of a speed option, temperat ure range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographic al error or incorrect specificati on. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local sales office.
publication number s25fl032p_00 revision 09 issue date january 29, 2013 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6v read and write operations ? memory architecture ? uniform 64 kb sectors ? top or bottom parameter block (two 64-kb sectors (top or bottom) broken down into sixteen 4-kb sub-sectors each) ? 256-byte page size ? backward compatible with the s25fl032a device ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? program operations are on a page by page basis ? accelerated programming mode via 9v w#/acc pin ? quad page programming ? erase ? bulk erase function ? sector erase (se) command (d8h) for 64 kb sectors ? sub-sector erase (p4e) command (20h) for 4 kb sectors ? sub-sector erase (p8e) command (40h) for 8 kb sectors ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? jedec standard two-byte electronic signature ? res command one-byte electronic signature for backward compatibility ? one time programmable (otp) area for permanent, secure identification; can be programmed and locked at the factory or by the customer ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? process technology ? manufactured on 0.09 m mirrorbit ? process technology ? package option ? industry standard pinouts ? 8-pin so package (208 mils) ? 16-pin so package (300 mils) ? 8-contact uson package (5 x 6 mm) ? 8-contact wson package (6 x 8 mm) ? 24-ball bga 6 x 8 mm package, 5 x 5 pin configuration ? 24-ball bga 6 x 8 mm package, 6 x 4 pin configuration performance characteristics ? speed ? normal read (seria l): 40 mhz clock rate ? fast_read (serial): 104 mhz clock rate (maximum) ? dual i/o fast_read: 80 mhz clock rate or 20 mb/s effective data rate ? quad i/o fast_read: 80 mhz clock rate or 40 mb/s effective data rate ? power saving standby mode ? standby mode 80 a (typical) ? deep power-down mode 3 a (typical) memory protection features ? memory protection ? w#/acc pin works in conjunction with status register bits to protect specified memory areas ? status register block protection bits (bp2, bp1, bp0) in status s25fl032p 32-mbit cmos 3.0 volt flash memory with 104-mhz spi (serial peripher al interface) multi i/o bus data sheet
4 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet general description the s25fl032p is a 3.0 volt (2.7v to 3.6v), single- power-supply flash memory device. the device consists of 64 uniform 64 kb sectors with the tw o (top or bottom) 64 kb sectors further split up into thirty-two 4kb sub sectors. the s25fl032p device is fully backward compatible with the s25fl032a device. the device accepts data written to si (serial input) and outputs data on so (serial output). the devices are designed to be programmed in-system wi th the standard syst em 3.0-volt v cc supply. the s25fl032p device adds the following high-per formance features using 5 new instructions: ? dual output read using both si and so pins as output pins at a clock rate of up to 80 mhz ? quad output read using si, so, w#/acc and hold# pins as output pins at a clock rate of up to 80 mhz ? dual i/o high performance read using both si and so pi ns as input and output pins at a clock rate of up to 80 mhz ? quad i/o high performance read using si, so, w#/acc and hold# pins as input and output pins at a clock rate of up to 80 mhz ? quad page programming using si, so, w#/acc and hold# pi ns as input pins to program data at a clock rate of up to 80 mhz the memory can be programmed 1 to 256 bytes at a time, using the page program command. the device supports sector erase and bulk erase commands. each device requires only a 3.0-volt power supply (2.7v to 3.6v) for both read and write functions. internally generated and regulated voltages are provided for the program o perations. this device requires a high voltage supply to the w#/acc pin to enable the accelerated programming mode. the s25fl032p device also offers a one-time progra mmable area (otp) of up to 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of otp space for other use. this otp area can be programmed or read using the otpp or otpr instructions.
january 29, 2013 s25fl032p_00_09 s25fl032p 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. spansion spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 byte or page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 quad page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 dual and quad i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 sector erase / bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 monitoring write operations using the status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 data protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10 hold mode (hold#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.11 accelerated programming operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 dual output read mode (dor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.4 quad output read mode (qor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5 dual i/o high performance read mode (dior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.6 quad i/o high performance read mode (qior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.7 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.8 read-id (read_id). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.9 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.10 write disable (wrdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.11 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.12 read configuration register (rcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.13 write registers (wrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.14 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.15 quad page program (qpp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 9.16 parameter sector erase (p4e, p8e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.17 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.18 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.19 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.20 release from deep power-down (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.21 clear status register (clsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.22 otp program (otpp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.23 read otp data bytes (otpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 10. otp regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.1 programming otp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2 reading otp data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3 locking otp regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11. power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12. initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 13. program acceleration via w#/acc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.1 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 19. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19.1 soc008 wide ? 8-pin plas tic small outline package (208-mils body width) . . . . . . . . . . . 61 19.2 so3 016 ? 16-pin wide plastic small outline pack age (300-mil body width) . . . . . . . . . . 62 19.3 une008 ? uson 8-contact (5 x 6 mm) no-lead package . . . . . . . . . . . . . . . . . . . . . . . . . 63 19.4 wnf008 ? wson 8-contact (6 x 8 mm) no-lead package . . . . . . . . . . . . . . . . . . . . . . . . 64 19.5 fab024 ? 24-ball ball grid array (6 x 8 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 19.6 fac024 ? 24-ball ball grid array (6 x 8 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
january 29, 2013 s25fl032p_00_09 s25fl032p 7 data sheet figures figure 2.1 16-pin plastic small outline package (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2.2 8-pin plastic small outline package (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2.3 8-contact uson (5 x 6 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2.4 8-contact wson package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2.5 6x8 mm 24-ball bga package, 5x5 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2.6 6x8 mm 24-ball bga package, 6x4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6.1 bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6.2 spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7.1 hold mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9.1 read data bytes (read) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9.2 read data bytes at higher speed (fast_read) command sequence . . . . . . . . . . . . . . . 25 figure 9.3 dual output read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9.4 quad output read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9.5 dual i/o high performance read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9.6 continuous dual i/o high pe rformance read instruction sequence . . . . . . . . . . . . . . . . . . 29 figure 9.7 quad i/o high performance instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 9.8 continuous quad i/o high pe rformance instruction sequence. . . . . . . . . . . . . . . . . . . . . . 31 figure 9.9 read identific ation (rdid) command sequence and data-out sequence . . . . . . . . . . . . . 32 figure 9.10 read-id (rdid) command timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9.11 write enable (wren) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9.12 write disable (wrdi) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9.13 read status register (rdsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9.14 read configuration re gister (rcr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 9.15 write registers (wrr) instruction sequence ? 8 data bits . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 9.16 write registers (wrr) instruct ion sequence ? 16 data bits . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 9.17 page program (pp) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 9.18 quad page program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 9.19 parameter sector erase (p4e, p8e) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9.20 sector erase (se) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 9.21 bulk erase (be) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 9.22 deep power-down (dp) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 9.23 release from deep power-down (res) command sequence . . . . . . . . . . . . . . . . . . . . . . . 47 figure 9.24 release from deep power-down and res command sequence . . . . . . . . . . . . . . . . . . . . 48 figure 9.25 clear status register (clsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 9.26 otp program instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 9.27 read otp instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 10.1 otp memory map - part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10.2 otp memory map - part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 11.1 power-up timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 11.2 power-down and voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 13.1 acc program acceleration timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 14.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 14.2 maximum positive overshoot waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 figure 17.1 ac measurements i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 18.1 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 18.2 spi mode 0 (0,0) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 18.3 spi mode 0 (0,0) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 18.4 hold# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 18.5 write protect setu p and hold timing during wrr when srwd = 1 . . . . . . . . . . . . . . . . . . 60
8 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet tables table 5.1 s25fl032p valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7.1 suggested cross settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7.2 configuration register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 7.3 tbprot = 0 (starts protection from top of array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7.4 tbprot=1 (starts protection from bottom of array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 8.1 s25fl032p sector address table tbparm=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 8.2 s25fl032p sector address table tbparm=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 9.1 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 9.2 manufacturer & device id - rdid (jedec 9fh): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 9.3 product group cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 table 9.4 product group cfi system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 table 9.5 product group cfi device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 9.6 product group cfi primary vendo r-specific extended query . . . . . . . . . . . . . . . . . . . . . . . .34 table 9.7 read_id data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 9.8 s25fl032p status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 9.9 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 10.1 esn1 and esn2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 11.1 power-up / power-down voltage and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 13.1 acc program acceleration specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 15.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 16.1 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 17.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
january 29, 2013 s25fl032p_00_09 s25fl032p 9 data sheet 1. block diagram 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) note dnc = do not connect (reserved for future use) s ram p s lo g ic array - l array - r rd data path io x d e c c s # s ck s i / io0 s o / io1 gnd hold# / io 3 v cc w# / acc / io2 1 2 3 4 16 15 14 1 3 hold#/io 3 vcc dnc dnc dnc dnc s i/io0 s ck 5 6 7 8 12 11 10 9 w#/acc/io2 gnd dnc dnc dnc dnc c s # s o/io1
10 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet figure 2.2 8-pin plastic small outline package (so) figure 2.3 8-contact uson (5 x 6 mm) package note there is an exposed central pad on the underside of the uson pack age. this should not be connected to any voltage or signal lin e on the pcb. connecting the central pad to gnd (v ss ) is possible, provided pcb routing ensures 0mv difference between voltage at the uson gnd (v ss ) lead and the central exposed pad. figure 2.4 8-contact wson package (6 x 8 mm) note there is an exposed central pad on the underside of the wson pack age. this should not be connected to any voltage or signal lin e on the pcb. connecting the central pad to gnd (v ss ) is possible, provided pcb routing ensures 0mv difference between voltage at the wson gnd (v ss ) lead and the central exposed pad. figure 2.5 6x8 mm 24-ball bga package, 5x5 pin configuration 1 2 3 4 c s # s o/io1 w#/acc/io2 gnd s i/io0 s ck hold#/io 3 vcc 5 6 7 8 1 2 3 4 5 6 7 8 cs# so/io1 hold#/io3 sck si/io0 gnd uson w#/acc/io2 vcc 1 2 3 4 5 6 7 8 cs# so/io1 hold#/io3 sck si/io0 gnd wson w#/acc/io2 vcc s ck nc nc gnd vcc nc b2 b 3 b4 b5 c s # nc w#/acc/io2 nc c1 c2 c 3 c4 c5 s o/io1 s i/io0 hold#/io 3 nc d1 d2 d 3 d4 d5 nc nc nc e1 e2 e 3 nc nc e4 e5 nc nc nc nc a2 a 3 a4 a5 b1 nc
january 29, 2013 s25fl032p_00_09 s25fl032p 11 data sheet figure 2.6 6x8 mm 24-ball bga package, 6x4 pin configuration 3. input/output descriptions s ck nc nc gnd vcc b2 b3 b4 c s # nc w#/acc/io2 c1 c2 c3 c4 s o/io1 s i/io0 hold#/io 3 d1 d2 d3 d4 nc nc nc e1 e2 e3 nc e4 nc nc nc a2 a3 a4 b1 nc nc nc nc f1 f2 f 3 nc f4 nc a1 signal i/o description so/io1 i/o serial data output : transfers data serially out of the device on the falling edge of sck. functions as an input pin in dual and quad i/o, and quad page program modes. si/io0 i/o serial data input : transfers data serially into the device. device latches commands, addresses, and program data on si on the rising edge of sck. functions as an output pin in dual and quad i/o mode. sck input serial clock : provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs# input chip select : places device in active power mode when driven low. deselects device and places so at high impedance when high. after power-up, device requires a falling edge on cs# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold#/io3 i/o hold : pauses any serial communication with the device without deselecting it. when driven low, so is at high impedance, and all input at si and sck are ig nored. requires that cs# also be driven low. functions as an output pin in quad i/o mode. w#/acc/io2 i/o write protect : protects the memory area specified by status register bits bp2:bp0. when driven low, prevents any program or erase command from altering the data in the protected memory area. functions as an output pin in quad i/o mode. v cc input supply voltage gnd input ground
12 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 4. logic symbol c s # s o/io1 w#/acc/io2 gnd s i/io0 s ck hold#/io 3 v cc
january 29, 2013 s25fl032p_00_09 s25fl032p 13 data sheet 5. ordering information the ordering part number is formed by a valid combination of the following: 5.1 valid combinations table 5.1 lists the valid combinations co nfigurations planned to be support ed in volume for this device. s25fl 032 p 0x m f i 00 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 03 = 6 x 4 pin configuration bga package 02 = 5 x 5 pin configuration bga package 01 = 8-pin so package / 8-contact uson package 00 = 16-pin so package / 8-contact wson package temperature range i = industrial (?40c to +85c) v = automotive in-cabin (?40c to +105c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 8-pin / 16-pin so package n = 8-contact uson / wson package b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed 0x = 104 mhz device technology p = 0.09 m mirrorbit ? process technology density 032 = 32 mbit device family s25fl spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 5.1 s25fl032p valid combinations s25fl032p valid combinations package marking base ordering part number speed option package & temperature model number packing type s25fl032p 0x mfi, nfi 00, 01 0, 1, 3 fl032p + (temp) + f mfv, nfv bhi 02, 03 0, 3 bhv
14 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 6. spansion spi modes a microcontroller can use either of its two spi modes to control spansi on spi flash memory devices: ? cpol = 0, cpha = 0 (mode 0) ? cpol = 1, cpha = 1 (mode 3) input data is latched in on the rising edge of sck, and output data is avail able from the falling edge of sck for both modes. when the bus master is in standby mode, sck is as shown in figure 6.2 for each of the two modes: ? sck remains at 0 for (cpol = 0, cpha = 0 mode 0) ? sck remains at 1 for (cpol = 1, cpha = 1 mode 3) figure 6.1 bus master and memory devices on the spi bus note the write protect/accelerated programming (w#/acc) and hold (hold#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. figure 6.2 spi modes supported s pi interf a ce with (cpol, cpha) = (0, 0) or (1, 1) b us m as ter c s3 c s 2c s 1 s pi memory device s pi memory device s pi memory device c s # hold# c s # hold# c s # hold# s ck s o s i s ck s o s i s ck s o s i s o s i s ck w#/acc w#/acc w#/acc m s b m s b s ck s ck s i s o cpha cpol 00 11 c s # mode 0 mode 3
january 29, 2013 s25fl032p_00_09 s25fl032p 15 data sheet 7. device operations all spansion spi devices accept and output data in bytes (8 bits at a time). the spi device is a slave device that supports an inactive clock while cs# is held low. 7.1 byte or page programming programming data requires two co mmands: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. the page program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. programming means that bits can eith er be left at 0, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 7.2 quad page programming the quad page program (qpp) instruction allows up to 256 bytes of data to be pr ogrammed using 4 pins as inputs at the same time, thus effe ctively quadrupling the dat a transfer rate, compared to the page program (pp) instruction. the write enabl e latch (wel) bit must be set to a 1 using the write enable (wren) command prior to issuing the qpp command. 7.3 dual and quad i/o mode the s25fl032p device supports dual and quad i/o operation when using the dual/quad output read mode and the dual/quad i/o high performanc e mode instructions. using the dual or quad i/o instructions allows data to be transferred to or from th e device at two to four times the rate of standard spi devices. when operating in the dual or quad i/o high performance mode (bbh or ebh instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be in put two or four address bits at a time. 7.4 sector erase / bulk erase the sector erase (se) and bulk erase (be) commands set all the bits in a sector or the entire memory array to 1. while bits can be individually programmed from 1 to 0, er asing bits from 0 to 1 must be done on a sector- wide (se) or array-wide ( be) level. in addition to the 64-kb sector eras e (se), the s25fl032p device also offers 4-kb parameter sector erase (p4e) and 8-kb parameter sector erase (p8e). 7.5 monitoring write operations using the status register the host system can determine when a write register, pr ogram, or erase operation is complete by monitoring the write in progress (wip) bit in the stat us register. the read from status register command provides the state of the wip bit. in addition, the s25fl032p device offers two additional bits in the status register (p_err, e_err) to indi cate whether a program or erase operation was a success or failure. 7.6 active power and standby power modes the device is enabled and in the active power mode when chip select (cs#) is low. when cs# is high, the device is disabled, but may still be in the active po wer mode until all program, erase, and write registers operations have completed. the dev ice then goes into the standby power mode, and power consumption drops to i sb . the deep power-down (dp) command provides addi tional data protection against inadvertent signals. after writing the dp command, the device ignores any further progr am or erase commands, and reduces its power consumption to i dp .
16 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 7.7 status register the status register c ontains the status and contro l bits that can be read or set by specific commands (see table 9.1 on page 23 ). these bits configure diff erent protection configurati ons and supply information of operation of the device. (for details see table 9.8, s25fl032p status register on page 37 ): ? write in progress (wip): indicates whether the device is performi ng a write registers, program or erase operation. ? write enable latch (wel): indicates the status of the internal write enable latch. ? block protect (bp2, bp1, bp0): non-volatile bits that define me mory area to be software-protected against program and erase commands. ? erase error (e_err): the erase error bit is used as an erase operation success and failure check. ? program error (p_err): the program error bit is used as an program operation success and failure check. ? status register write disable (srwd): places the device in the hardware protected mode when this bit is set to 1 and the w#/acc input is driven low. in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits. 7.8 configuration register the configuration regist er contains the control bits that can be read or set by specific commands. these bits configure different configurations and security features of the device. ? the freeze bit locks the bp2-0 bits in status register and the tbprot and tbparm bits in the configuration register. note that once the freeze bit has been set to ?1?, then it cannot be cleared to ?0? until a power-on-reset is executed. as long as the fr eeze bit is set to ?0?, then the other bits of the configuration register, including freeze bit, can be written to. ? the quad bit is non-volatile and sets the pin out of the device to quad mode; that is, w#/acc becomes io2 and hold# becomes io3. the instructions for seri al, dual output, and dual i/o reads function as normal. the w#/acc and hold# functionality does not work when the device is set in quad mode. ? the tbparm bit defines the logical location of the 4 kb parameter sect ors. the parameter sectors consist of thirty two 4 kb sectors. all sectors other than th e parameter sectors are defined to be 64-kb uniform in size. when tbparm is set to a ?1?, the 4 kb paramet er sectors starts at the top of the array. when tbparm is set to a ?0?, the 4 kb parameter sectors starts at the bottom of the array. note that once this bit is set to a '1', it cannot be changed back to '0'. ? the bpnv bit defines whether or not the bp2-0 bits in the status register are volatile or non-volatile. when bpnv is set to a ?1?, the bp2-0 bits in the status register are volatile and will be reset to binary 111 after power on reset. when bpnv is set to a ?0?, the bp2-0 bits in the status register are non-volatile. note that once this bit is set to a '1', it cannot be changed back to '0'. ? the tbprot bit defines the operation of the bloc k protection bits bp2, bp1, and bp0 in the status register. when tbprot is set to a ?0?, then the block pr otection is defined to start fr om the top of the array. when tbprot is set to a ?1?, then the block protection is defined to start from the bottom of the array. note that once this bit is set to a '1', it cannot be changed back to '0'. note : it is suggested that the block protection and para meter sectors not be set to the same area of the array; otherwise, the user cannot ut ilize the parameter sectors if they are protected. the following matrix shows the recommended settings. table 7.1 suggested cross settings tbparm tbprot array overview 00 parameter sectors ? bottom bp protection ? top (default) 0 1 not recommended (parameters & bp protection are both bottom) 1 0 not recommended (parameters & bp protection are both top) 11 parameter sectors - top of array (high address) bp protection - bottom of array (low address)
january 29, 2013 s25fl032p_00_09 s25fl032p 17 data sheet note (default) indicates the value of each configuration register bit set upon initial factory shipment. 7.9 data protection modes spansion spi flash memory devices provi de the following data protection methods: ? the write enable (wren) command: must be written prior to any co mmand that modifies data. the wren command sets the write enable latch (wel) bit. the wel bit resets (disables writes) on power-up or after the device completes the following commands: ? page program (pp) ? sector erase (se) ? bulk erase (be) ? write disable (wrdi) ? write register (wrr) ? parameter 4 kb sector erase (p4e) ? parameter 8 kb sector erase (p8e) ? quad page programming (qpp) ? otp byte programming (otpp) ? software protected mode (spm): the block protect (bp2, bp1, bp0) bits define the section of the memory array that can be read but not programmed or erased. table 7.3 and table 7.4 shows the sizes and address ranges of protected areas that ar e defined by status register bits bp2:bp0. ? hardware protected mode (hpm): the write protect (w#/acc) inpu t and the status register write disable (srwd) bit together provide write protection. ? clock pulse count: the device verifies that all program, eras e, and write register commands consist of a clock pulse count that is a multip le of eight before executing them. table 7.2 configuration register table bit bit name bit function description 7 na - not used 6 na - not used 5 tbprot configures start of block protection 1 = bottom array (low address) 0 = top array (high address) (default) 4 na - do not use 3 bpnv configures bp2-0 bits in the status register 1 = volatile 0 = non-volatile (default) 2 tbparm configures parameter sector location 1 = top array (high address) 0 = bottom array (low address) (default) 1 quad puts the device into quad i/o mode 1 = quad i/o 0 = dual or serial i/o (default) 0 freeze locks bp2-0 bits in the status register 1 = enabled 0 = disabled (default)
18 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 7.10 hold mode (hold#) the hold input (hold#) stops any se rial communication with the device, but does not terminate any write registers, program or erase operation that is currently in progress. the hold mode starts on the falling edge of hold# if sck is also low (see figure 7.1 , standard use). if the falling edge of hold# does not occur while sck is low, the hold mode begins after the next falling edge of sck (non-standard use). the hold mode ends on the rising edge of hold# signal (s tandard use) if sck is also low. if the rising edge of hold# does not occur while sc k is low, the hold mode ends on the next falling edge of clk (non- standard use) see figure 7.1 . the so output is high impedance, and the si and sck in puts are ignored (don?t care ) for the duration of the hold mode. cs# must remain low for the entire duration of the hold mode to ensure that the devi ce internal logic remains unchanged. if cs# goes high while the device is in the ho ld mode, the internal logic is reset. to prevent the device from reverting to the hold mode when device co mmunication is resumed, ho ld# must be held high, followed by driving cs# low. note: the hold mode feature is disabled during quad i/o mode. table 7.3 tbprot = 0 (starts protection from top of array) status register block memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0 0 0 none 0 000000h-3fffffh sa63:sa0 0 0 0 1 3f0000h-3fffffh (1) sa63 000000h-3effffh sa62:sa0 1/64 0 1 0 3e0000h-3fffffh (2) sa63:sa62 000000h-3dffffh sa61:sa0 1/32 0 1 1 3c0000h-3fffffh (4) sa63:sa60 000000h-3bffffh sa59:sa0 1/16 1 0 0 380000h-3fffffh (8) sa63:sa56 000000h-37ffffh sa55:sa0 1/8 1 0 1 300000h-3fffffh (16) sa63:sa48 000000h-2fffffh sa47:sa0 1/4 1 1 0 200000h-3fffffh (32) sa63:sa32 000000h-1fffffh sa31:sa0 1/2 1 1 1 000000h-3fffffh (64) sa63:sa0 none none all table 7.4 tbprot=1 (starts protection from bottom of array) status register block memory array protected portion of total memory area bp2 bp1 bp0 protected address range protected sectors unprotected address range unprotected sectors 0 0 0 none 0 000000h-3fffffh sa0:sa63 0 0 0 1 000000h-00ffffh (1) sa0 010000h-3fffffh sa1:sa63 1/64 0 1 0 000000h-01ffffh (2) sa0:sa1 020000h-3fffffh sa2:sa63 1/32 0 1 1 000000h-03ffffh (4) sa0:sa3 040000h-3fffffh sa4:sa63 1/16 1 0 0 000000h-07ffffh (8) sa0:sa7 080000h-3fffffh sa8:sa63 1/8 1 0 1 000000h-0fffffh (16) sa0:sa15 100000h-3fffffh sa16:sa63 1/4 1 1 0 000000h-1fffffh (32) sa0:sa31 200000h-3fffffh sa32:sa63 1/2 1 1 1 000000h-3fffffh (64) sa0:sa63 none none all
january 29, 2013 s25fl032p_00_09 s25fl032p 19 data sheet figure 7.1 hold mode operation 7.11 accelerated progr amming operation the device offers accelerated program operations thro ugh the acc function. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device uses the higher voltage on the pin to reduce the time required for program operations. removing v hh from the w#/acc pin returns the device to normal opera tion. note that the w#/a cc pin must not be at v hh for operations other t han accelerated programming, or device damage may result. in addition, the w#/acc pin must not be left fl oating or unconnected; inco nsistent behavior of the device may result. note : the acc function is di sabled during quad i/o mode. s ck hold# hold condition ( s t a nd a rd us e) hold condition (non- s t a nd a rd us e)
20 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 8. sector address table the sector address tables show the size of the memory array, sectors, and pages. the device uses pages to cache the program data before the data is programmed into the memory array. each page or byte can be individually programmed (bits are changed from 1 to 0). the data is er ased (bits are changed from 0 to 1) on a sub-sector, sector- or device-wide basis using the p4e/p8e, se or be commands. table 8.1 and table 8.2 show the starting and ending address for each sector . the complete set of sectors comprises the memory array of the flash device. note sector sa0 is split up into sub-sectors ss0 - ss15 (dark gray shading) sector sa1 is split up into sub-se ctors ss16 - ss31(light gray shading) table 8.1 s25fl032p sector address table tbparm=0 sector address range sector address range sector address range start address end address start address end address start address end address sa63 3f0000h 3fffffh sa31 1f0000h 1fffffh ss31 01f000h 01ffffh sa62 3e0000h 3effffh sa30 1e0000h 1effffh ss30 01e000h 01efffh sa61 3d0000h 3dffffh sa29 1d0000h 1dffffh ss29 01d000h 01dfffh sa60 3c0000h 3cffffh sa28 1c0000h 1cffffh ss28 01c000h 01cfffh sa59 3b0000h 3bffffh sa27 1b0000h 1bffffh ss27 01b000h 01bfffh sa58 3a0000h 3affffh sa26 1a0000h 1affffh ss26 01a000h 01afffh sa57 390000h 39ffffh sa25 190000h 19ffffh ss25 019000h 019fffh sa56 380000h 38ffffh sa24 180000h 18ffffh ss24 018000h 018fffh sa55 370000h 37ffffh sa23 170000h 17ffffh ss23 017000h 017fffh sa54 360000h 36ffffh sa22 160000h 16ffffh ss22 016000h 016fffh sa53 350000h 35ffffh sa21 150000h 15ffffh ss21 015000h 015fffh sa52 340000h 34ffffh sa20 140000h 14ffffh ss20 014000h 014fffh sa51 330000h 33ffffh sa19 130000h 13ffffh ss19 013000h 013fffh sa50 320000h 32ffffh sa18 120000h 12ffffh ss18 012000h 012fffh sa49 310000h 31ffffh sa17 110000h 11ffffh ss17 011000h 011fffh sa48 300000h 30ffffh sa16 100000h 10ffffh ss16 010000h 010fffh sa47 2f0000h 2fffffh sa15 0f0000h 0fffffh ss15 00f000h 00ffffh sa46 2e0000h 2effffh sa14 0e0000h 0effffh ss14 00e000h 00efffh sa45 2d0000h 2dffffh sa13 0d0000h 0dffffh ss13 00d000h 00dfffh sa44 2c0000h 2cffffh sa12 0c0000h 0cffffh ss12 00c000h 00cfffh sa43 2b0000h 2bffffh sa11 0b0000h 0bffffh ss11 00b000h 00bfffh sa42 2a0000h 2affffh sa10 0a0000h 0affffh ss10 00a000h 00afffh sa41 290000h 29ffffh sa9 090000h 09ffffh ss9 009000h 009fffh sa40 280000h 28ffffh sa8 080000h 08ffffh ss8 008000h 008fffh sa39 270000h 27ffffh sa7 070000h 07ffffh ss7 007000h 007fffh sa38 260000h 26ffffh sa6 060000h 06ffffh ss6 006000h 006fffh sa37 250000h 25ffffh sa5 050000h 05ffffh ss5 005000h 005fffh sa36 240000h 24ffffh sa4 040000h 04ffffh ss4 004000h 004fffh sa35 230000h 23ffffh sa3 030000h 03ffffh ss3 003000h 003fffh sa34 220000h 22ffffh sa2 020000h 02ffffh ss2 002000h 002fffh sa33 210000h 21ffffh sa1 010000h 01ffffh ss1 001000h 001fffh sa32 200000h 20ffffh sa0 000000h 00ffffh ss0 000000h 000fffh
january 29, 2013 s25fl032p_00_09 s25fl032p 21 data sheet note sector sa62 is split up into sub-se ctors ss0 - ss15 (dark gray shading) sector sa63 is split up into sub-se ctors ss16 - ss31 (light gray shading) table 8.2 s25fl032p sector address table tbparm=1 sector address range sector address range sector address range start address end address start address end address start address end address ss31 3ff000h 3fffffh sa63 3f0000h 3fffffh sa31 1f0000h 1fffffh ss30 3fe000h 3fefffh sa62 3e0000h 3effffh sa30 1e0000h 1effffh ss29 3fd000h 3fdfffh sa61 3d0000h 3dffffh sa29 1d0000h 1dffffh ss28 3fc000h 3fcfffh sa60 3c0000h 3cffffh sa28 1c0000h 1cffffh ss27 3fb000h 3fbfffh sa59 3b0000h 3bffffh sa27 1b0000h 1bffffh ss26 3fa000h 3fafffh sa58 3a0000h 3affffh sa26 1a0000h 1affffh ss25 3f9000h 3f9fffh sa57 390000h 39ffffh sa25 190000h 19ffffh ss24 3f8000h 3f8fffh sa56 380000h 38ffffh sa24 180000h 18ffffh ss23 3f7000h 3f7fffh sa55 370000h 37ffffh sa23 170000h 17ffffh ss22 3f6000h 3f6fffh sa54 360000h 36ffffh sa22 160000h 16ffffh ss21 3f5000h 3f5fffh sa53 350000h 35ffffh sa21 150000h 15ffffh ss20 3f4000h 3f4fffh sa52 340000h 34ffffh sa20 140000h 14ffffh ss19 3f3000h 3f3fffh sa51 330000h 33ffffh sa19 130000h 13ffffh ss18 3f2000h 3f2fffh sa50 320000h 32ffffh sa18 120000h 12ffffh ss17 3f1000h 3f1fffh sa49 310000h 31ffffh sa17 110000h 11ffffh ss16 3f0000h 3f0fffh sa48 300000h 30ffffh sa16 100000h 10ffffh ss15 3ef000h 3effffh sa47 2f0000h 2fffffh sa15 0f0000h 0fffffh ss14 3ee000h 3eefffh sa46 2e0000h 2effffh sa14 0e0000h 0effffh ss13 3ed000h 3edfffh sa45 2d0000h 2dffffh sa13 0d0000h 0dffffh ss12 3ec000h 3ecfffh sa44 2c0000h 2cffffh sa12 0c0000h 0cffffh ss11 3eb000h 3ebfffh sa43 2b0000h 2bffffh sa11 0b0000h 0bffffh ss10 3ea000h 3eafffh sa42 2a0000h 2affffh sa10 0a0000h 0affffh ss9 3e9000h 3e9fffh sa41 290000h 29ffffh sa9 090000h 09ffffh ss8 3e8000h 3e8fffh sa40 280000h 28ffffh sa8 080000h 08ffffh ss7 3e7000h 3e7fffh sa39 270000h 27ffffh sa7 070000h 07ffffh ss6 3e6000h 3e6fffh sa38 260000h 26ffffh sa6 060000h 06ffffh ss5 3e5000h 3e5fffh sa37 250000h 25ffffh sa5 050000h 05ffffh ss4 3e4000h 3e4fffh sa36 240000h 24ffffh sa4 040000h 04ffffh ss3 3e3000h 3e3fffh sa35 230000h 23ffffh sa3 030000h 03ffffh ss2 3e2000h 3e2fffh sa34 220000h 22ffffh sa2 020000h 02ffffh ss1 3e1000h 3e1fffh sa33 210000h 21ffffh sa1 010000h 01ffffh ss0 3e0000h 3e0fffh sa32 200000h 20ffffh sa0 000000h 00ffffh
22 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9. command definitions the host system must shift all commands, addresses, and data in and out of the de vice, beginning with the most significant bit. on the first rising edge of sck after cs# is driven low, the device accepts the one-byte command on si (all commands are one byte long), most si gnificant bit first. each successive bit is latched on the rising edge of sck. table 9.1 lists the complete set of commands. every command sequence begins with a one-byte command code. the command may be followed by address, data, both, or nothing, depending on the command. cs# must be driven high after the last bit of the command sequence has been written. the read data bytes (read), read data bytes at hi gher speed (fast_read), dual output read (dor), quad output read (qor), dual i/o high performance read (dior), quad i/o high performance read (qior), read status regi ster (rdsr), read confi guration register (rcr), read otp data (otpr), read manufacturer and device id (read_i d), read identificati on (rdid) and release from deep power-down and read electronic signatur e (res) command sequences are followed by a data output sequence on so. cs# can be driven high after any bit of the s equence is output to terminate the operation. the page program (pp), quad page program (qpp), 64 kb sector erase (se), 4 kb parameter sector erase (p4e), 8 kb parameter sector erase (p8e), bulk erase (be), write status and configuration registers (wrr), program otp space (otpp), write enable (wren) , or write disable (wrdi) commands require that cs# be driven high at a byte boundary, otherwise the command is not exec uted. since a byte is composed of eight bits, cs# must therefore be driven high when the numbe r of clock pulses after cs# is driven low is an exact multiple of eight. the device ignores any attempt to access the memory array during a write regist ers, program, or erase operation, and continues the operation uninterrupted. the instruction set is listed in table 9.1 .
january 29, 2013 s25fl032p_00_09 s25fl032p 23 data sheet table 9.1 instruction set operation command one byte command code description address byte cycle mode bit cycle dummy byte cycle data byte cycle read read (03h) 0000 0011 read data bytes 3 0 0 1 to fast_read (0bh) 0000 1011 read data bytes at fast speed 3 0 1 1 to dor (3bh) 0011 1011 dual output read 3 0 1 1 to qor (6bh) 0110 1011 quad output read 3 0 1 1 to dior (bbh) 1011 1011 dual i/o high performance read 3 1 0 1 to qior (ebh) 1110 1011 quad i/o high performance read 3 1 2 1 to rdid (9fh) 1001 1111 read identification 0 0 0 1 to 81 read_id (90h) 1001 0000 read manufacturer and device identification 3 0 0 1 to write control wren (06h) 0000 0110 write enable 0 0 0 0 wrdi (04h) 0000 0100 write disable 0 0 0 0 erase p4e (20h) 0010 0000 4 kb parameter sector erase 3 0 0 0 p8e (40h) 0100 0000 8 kb (two 4kb) parameter sector erase 3 0 0 0 se (d8h) 1101 1000 64kb sector erase 3 0 0 0 be (60h) 0110 0000 or (c7h) 1100 0111 bulk erase 0 0 0 0 program pp (02h) 0000 0010 page programming 3 0 0 1 to 256 qpp (32h) 0011 0010 quad page programming 3 0 0 1 to 256 status & configuration register rdsr (05h) 0000 0101 read status register 0 0 0 1 to wrr (01h) 0000 0001 write (status & configuration) register 0 0 0 1 to 2 rcr (35h) 0011 0101 read configuration register (cfg) 0 0 0 1 to clsr (30h) 0011 0000 reset the erase and program fail flag (sr5 and sr6) and restore normal operation) 0000 power saving dp (b9h) 1011 1001 deep power-down 0 0 0 0 res (abh) 1010 1011 release from deep power-down mode 0 0 0 0 (abh) 1010 1011 release from deep power-down and read electronic signature 0031 to otp otpp (42h) 0100 0010 program one byte of data in otp memory space 3 0 0 1 otpr (4bh) 0100 1011 read data in the otp memory space 3 0 1 1 to
24 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.1 read data bytes (read) the read data bytes (read) command reads data from the memory array at the frequency (f r ) presented at the sck input, with a maximum speed of 40 mhz. the host system must first select the device by driving cs# low. the read command is then written to si, followed by a 3 byte address (a23-a0). each bit is latched on the rising edge of sck. the memory array data, at t hat address, are output seri ally on so at a frequency f r , on the falling edge of sck. figure 9.1 and table 9.1 on page 23 detail the read command sequence. the first address byte specified can start at any location of the memo ry array. the device aut omatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single read command. when the highest address is reached, the address c ounter reverts to 00000h , allowing the read sequence to continue indefinitely. the read command is terminated by driving cs# high at any time during data output . the device rejects any read command issued while it is executing a program, erase, or write register s operation, and continues the operation uninterrupted. figure 9.1 read data bytes (read) command sequence comm a nd 24 bit addre ss hi-z m s b m s b d a t a o u t 1 d a t a o u t 2 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 3 0 29 2 8 10 9 8 7 6 5 4 3 2 1 7 6 5 2 3 22 21 4 3 2 1 0 3 2 10 7 s o s i s ck c s # mode 3 mode 0
january 29, 2013 s25fl032p_00_09 s25fl032p 25 data sheet 9.2 read data bytes at higher speed (fast_read) the fast_read command reads data from the memory array at the frequency (f c ) presented at the sck input, with a maximum speed of 104 mhz. the host system must first select the device by driving cs# low. the fast_read command is then written to si, followed by a 3 byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. the me mory array data, at that address, are output serially on so at a frequency f c , on the falling edge of sck. the fast_read command sequence is shown in figure 9.2 and table 9.1 on page 23 . the first address byte specified can start at any location of the memory array. the device automati cally increments to the next higher address after each byte of data is output. the entire memory array can ther efore be read with a single fast_read command. when the highest address is reached, the address count er reverts to 000000h, allowing the read sequence to continue indefinitely. the fast_read command is terminated by driving cs # high at any time during data output. the device rejects any fast_read command issued while it is executing a program, eras e, or write registers operation, and continues the operation uninterrupted. figure 9.2 read data bytes at higher speed (fast_read) command sequence c s # s ck s i s o comm a nd 24 bit addre ss d u mmy byte hi-z data out 1 data out 2 m s b m s b 01 2 3 4 56 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 2 3 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7 mode 3 mode 0
26 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.3 dual output read mode (dor) the dual output read instruction is similar to the fast_read instruction, except that the data is shifted out 2 bits at a time using 2 pins (si/io0 and so/io1) inst ead of 1 bit, at a maximum frequency of 80 mhz. the dual output read mode effectively doubles the data transfer rate compared to the fast_read instruction. the host system must first select the device by driv ing cs# low. the dual output read command is then written to si, followed by a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. then the memory contents, at the address that is given, are shifted out two bi ts at a time through the io0 (si) and io1 (so) pins at a frequency f c on the falling edge of sck. the dual output read command sequence is shown in figure 9.3 and table 9.1 on page 23 . the first address byte specified can star t at any location of the memory array. the device automatically increments to the next higher address after each byte of data is outp ut. the entire memory array can therefore be read with a single dual output read command. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. it is important t hat the i/o pins be set to hi gh-impedance prior to the falling edge of the first data out clock. the dual output read command is terminated by driving cs# high at any ti me during data output. the device rejects any dual output read command issued wh ile it is executing a program, erase, or write registers operation, and continues the oper ation uninterrupted. figure 9.3 dual output read instruction sequence c s # s ck s o/io1 s i s witche s from inp u t to o u tp u t 24 bit addre ss d u mmy byte hi-z byte 2 *m s b 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 94041424 3 44 45 46 47 2 3 * 22 21 3 2107 * 654 3 210 6420 s i/io0 012 3 4 56 7 8 9 10 in s tr u ction byte 1 7 5 3 1 7 * 5 3 1 7 * 6420 6
january 29, 2013 s25fl032p_00_09 s25fl032p 27 data sheet 9.4 quad output read mode (qor) the quad output read instruction is si milar to the fast_read instruction, except that the dat a is shifted out 4 bits at a time using 4 pins (si/io0, so/io1, w# /acc/io2 and hold#/io3) instead of 1 bit, at a maximum frequency of 80 mhz. the quad output read mode effectively doubles the da ta transfer rate compared to the dual output read instruction, and is four times the data transfer rate of the fast_read instruction. the host system must first select the device by dr iving cs# low. the quad ou tput read command is then written to si, followed by a 3-byte address (a23-a0) and a dummy byte. each bit is latched on the rising edge of sck. then the memory cont ents, at the address that are given, are shifted out four bits at a time through io0 (si), io1 (so), io2 (w#/acc), and io3 (hold#) pins at a frequency f c on the falling edge of sck. the quad output read command sequence is shown in figure 9.4 and table 9.1 on page 23 . the first address byte specified can star t at any location of the memory array. the device automatically increments to the next higher address after each byte of data is outp ut. the entire memory array can therefore be read with a single quad output read command. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. it is important t hat the i/o pins be set to hi gh-impedance prior to the falling edge of the first data out clock. the quad output read command is terminated by dr iving cs# high at any time during data output. the device rejects any quad output read command issued wh ile it is executing a pr ogram, erase, or write registers operation, and continues the oper ation uninterrupted. the quad bit of configuration regist er must be set (cr bit1 = 1) to enabl e the quad mode capability of the s25fl device. figure 9.4 quad output read instruction sequence c s # s ck s i/io0 s o/io1 w#/acc/io2 hold#/io 3 s i s witche s from inp u t to o u tp u t 24 bit addre ss d u mmy byte hi-z *m s b 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 94041424 3 44 45 46 47 2 3 * 22 21 3 2107654 3 2 * 10 4 012 3 4567 8 910 in s tr u ction 51 7 * 5 3 4 2 0 6 hi-z hi-z data out 1 data out 2 data out 3 data out 4 7 * 3 7 * 3 7 * 3 7 * 2 6 2 6 2 6 6 51 5151 4 0 4 0 4 0
28 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.5 dual i/o high performa nce read mode (dior) the dual i/o high performance read instruction is similar to the dual output read inst ruction, except that it improves throughput by allowing input of the address bi ts (a23-a0) using 2 bits per sck via two input pins (si/io2 and so/io1), at a ma ximum frequency of 80 mhz. the host system must first select the device by dr iving cs# low. the dual i/ o high performance read command is then written to si, followed by a 3-byte address (a23-a0) and a 1-byte mode instruction, with two bits latched on the rising edge of sck. then the memory c ontents, at the addre ss that is given, are shifted out two bits at a time through io0 (si) and io1 (so). the dual i/o high performance read command sequence is shown in figure 9.5 and table 9.1 on page 23 . the first address byte specified can start at any location of the memory array. the device automatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single dual i/o hi gh performance read co mmand. when the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. in addition, address jumps can be done without exiting the dual i/o high performance mode through the setting of the mode bits (after the address (a23-0) sequence, as shown in figure 9.5 ). this added feature removes the need for the instructio n sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits contro l the length of the next dual i/o hi gh performance instruction through the inclusion or exclusion of the first by te instruction code. the lower nibble (b its 3-0) of the mode bits are don?t care (?x?). if the mode bits equal axh, then the dev ice remains in dual i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted lo w) without requiring the bbh instruction opcode, as shown in figure 9.6 , thus eliminating eight cycles for the instruction sequence. however, if the mode bits are any va lue other than axh, then the next instru ction (after cs# is raised high and then asserted low) requires the instru ction sequence, which is normal operat ion. the following sequences will release the device from dual i/o high performance r ead mode; after which, the device can accept standard spi instructions: 1. during the dual i/o high performance instructi on sequence, if the mode bits are any value other than axh, then the next time cs# is raised high and then asserted low, the device will be released from dual i/o high performance read mode. 2. furthermore, during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0 & io1) are not set for a valid inst ruction sequence, then the device will be released from dual i/o high performance read mode. it is important t hat the i/o pins be set to hi gh-impedance prior to the falling edge of the first data out clock. the read instruction can be terminated by driving the cs# pin to the logi c high state. the cs# pin can be driven high at any time during data output to terminate a read operation. figure 9.5 dual i/o high performance read instruction sequence c s # s ck s o/io1 io0 & io1 s witche s from inp u t to o u tp u t 24 bit addre ss mode bit s hi-z byte 2 *m s b 2 8 29 3 0 3 1 1 8 19 20 21 22 2 3 24 25 26 27 2 3 * 22 21 3 2 1 0 7 * 6 5 4 s i/io0 012 3 4567 8 910 in s tr u ction byte 1 7 * 7 * 6 20 7 * 3 1 5 3 1 5 3 1 2 0 6 4 2 0 6 4 2 0
january 29, 2013 s25fl032p_00_09 s25fl032p 29 data sheet figure 9.6 continuous dual i/o high perfor mance read instruction sequence c s # s ck s o/io1 io0 & io1 s witche s from inp u t to o u tp u t 24 bit addre ss mode bit s byte 2 *m s b 21 22 2 3 11 12 1 3 14 15 16 17 1 8 19 20 2 3 * 22 21 3 2 1 0 7 * 6 5 4 s i/io0 01 910 byte 1 7 * 7 * 6 20 7 * 3 1 20 64 2 0 64 2 0 5 3 1 5 3 1
30 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.6 quad i/o high performance read mode (qior) the quad i/o high performance read instruction is simi lar to the quad output read instruction, except that it further improves throughput by al lowing input of the address bits (a23- a0) using 4 bits per sck via four input pins (si/io0, so/io1, w#/acc/io2 and hold #/io3), at a maximum frequency of 80 mhz. the host system must first select the device by driving cs# low. the quad i/o high performance read command is then written to si, followed by a 3-byte add ress (a23-a0) and a 1-byte m ode instruction, with four bits latched on the rising edge of sck. note that four dummy clocks are required pr ior to the data input. then the memory contents, at the address th at is given, are shift ed out four bits at a time through io0 (si), io1 (so), io2 (w#/acc), and io3 (hold#). the quad i/o high performance read command sequence is shown in figure 9.7 and table 9.1 on page 23 . the first address byte specified can start at any locati on of the memory array. the device automatically increments to the next higher address after each byte of data is output. the entire memory array can therefore be read with a single quad i/o high performance read comm and. when the highest address is reached, the address counter revert s to 00000h, allowing the read s equence to conti nue indefinitely. in addition, address jumps can be done without exiting th e quad i/o high performance mode through the setting of the mode bits (after the address (a23-0) sequence, as shown in figure 9.7 ). this added feature the removes the need for the instructio n sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits contro l the length of the next quad i/o high performance instru ction through the inclusion or exclusion of the first by te instruction code. the lower nibble (b its 3-0) of the mode bits are don't care (?x?). if the mode bits equal axh, then the device remains in quad i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted lo w) without requiring the ebh instruction opcode, as shown in figure 9.8 , thus eliminating eight cycles for the instruction sequence. the following sequences will release the device from quad i/o high performance read mode; after which, the device can accept standard spi instructions: 1. during the quad i/o high performance instructio n sequence, if the mode bits are any value other than axh, then the next time cs# is raised hi gh and then asserted low the device will be released from quad i/o high performance read mode. 2. furthermore, during any operation, if cs# toggles high to low to high for eight cycles (or less) and data input (io0, io1, io2, & io3) are not set for a valid instruction sequence, then the device will be released from quad i/o high performance read mode. it is important t hat the i/o pins be set to hi gh-impedance prior to the falling edge of the first data out clock. the read instruction can be terminated by driving the cs# pin to the logi c high state. the cs# pin can be driven high at any time during data output to terminate a read operation. figure 9.7 quad i/o high perform ance instruction sequence c s # s ck s o/io1 io ?s s witche s from inp u t to o u tp u t 24 bit addre ss mode bit s hi-z byte 2 *m s b 2 3 24 25 26 1 3 14 15 16 17 1 8 19 20 21 22 2 3 * 19 2 1 0 6 5 4 s i/io0 012 3 4567 8 9 in s tr u ction byte 1 7 * 6 7 * 3 5 3 1 2 0 4 dummy dummy hi-z hi-z w#/acc/io2 hold#/io 3 22 1 8 21 17 20 16 7 * 3 7 * 3 6 2 6 2 5 1 5 1 4 0 4 0
january 29, 2013 s25fl032p_00_09 s25fl032p 31 data sheet figure 9.8 continuous quad i/o high perf ormance instruction sequence 9.7 read identification (rdid) the read identification (rdid) comma nd outputs the one-byte manufacturer identification, followed by the two-byte device identification and t he bytes for the common flash interface (cfi) tables. the manufacturer identification is assigned by jedec; for spansion devices, it is 01h. the device identification (2 bytes) and cfi bytes are assigned by the device manufacturer. see table 9.2 on page 32 for device id data. the common flash interface (cfi) specification out lines device and host system software interrogation handshake, which allows vendor-specified software algor ithms to be used for enti re families of devices. software support can then be device-independent, jedec id-independent, and forward- and backward- compatible for the specified flash device families. flas h vendors can standardize their existing interfaces for long-term compatibility. the system can read cfi information at the addresses given in table 9.3 . the host system must first select the device by driv ing cs# low. the rdid command is then written to si, and each bit is latched on the rising edge of sck. one by te of manufacture identific ation, two bytes of device identification and sixty- six bytes of extended device identification are t hen output from the memory array on so at a frequency f r , on the falling edge of sck. the maximu m clock frequency for the rdid (9fh) command is 50 mhz (normal read). the manufacturer id and device id can be read repeatedly by applying multiples of 648 clock cycles. the manufacturer id, de vice id and cfi table can be continuously read as long as cs# is held low with a clock input. the rdid command sequence is shown in figure 9.9 and table 9.1 on page 23 . driving cs# high after the device identification da ta has been read at least once terminates the rdid command. driving cs# high at any time during data out put (for example, while reading the extended cfi bytes), also terminates the rdid operation. the device rejects any rdid command issued while it is executing a program, er ase, or write registers operation, and continues the operation uninterrupted. *ms b c s # s ck s o/io1 io ?s s witche s from inp u t to o u tp u t 24 bit addre ss mode bit s byte 2 1 3 14 15 16 2 3 * 19 2 1 0 6 5 4 s i/io0 01 4567 8 9 byte 1 7 * 6 7 * 3 5 3 1 2 0 4 dummy dummy w#/acc/io2 hold#/io 3 22 1 8 21 17 20 16 7 * 3 7 * 3 6 2 6 2 5 1 5 1 4 0 4 0 10 11 12
32 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet figure 9.9 read identification (rdid) comm and sequence and data-out sequence notes 1. byte 0 is manufacturer id of spansion. 2. byte 1 & 2 is device id. 3. byte 3 is extended device information string length, to indi cate how many extended device information bytes will follow. 4. bytes 4, 5 and 6 are spansion reserved (do not use). 5. for bytes 07h-0fh and 3dh-3fh, the data will be read as 0xff. 6. bytes 10h-50h are factory programmed per jedec standard. table 9.2 manufacturer & device id - rdid (jedec 9fh): device manuf. id device id # extended bytes byte 0 byte 1 byte 2 byte 3 s25fl032p spi flash 01h 02h 15h 4dh table 9.3 product group cfi query identification string byte data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set 15h 16h 40h 00h address for primary extended table 17h 18h 00h 00h alternate oem command set (00h = none exists) 19h 1ah 00h 00h address for alternate oem extended table (00h = none exists) table 9.4 product group cfi syst em interface string byte data description 1bh 27h v cc min. (erase/program): (d7-d4: volt, d3-d0: 100 mv) 1ch 36h v cc max. (erase/program): (d7-d4: volt, d3-d0: 100 mv) 1dh 00h v pp min. voltage (00h = no vpp pin present) 1eh 00h v pp max. voltage (00h = no vpp pin present) 1fh 0bh typical timeout per single byte program 2 n s 20h 0bh typical timeout for min. size page program 2 n s (00h = not supported) 21h 09h typical timeout per individual sector erase 2 n ms
january 29, 2013 s25fl032p_00_09 s25fl032p 33 data sheet 22h 0fh typical timeout for full chip erase 2 n ms (00h = not supported) 23h 01h max. timeout for byte program 2 n times typical 24h 01h max. timeout for page program 2 n times typical 25h 02h max. timeout per individual sector erase 2 n times typical 26h 01h max. timeout for full chip erase 2 n times typical (00h = not supported) table 9.4 product group cfi syst em interface string table 9.5 product group cfi device geometry definition byte data description 27h 16h device size = 2 n byte; 28h 05h flash device interface description; 00h = x8 only 01h = x16 only 02h = x8/x16 capable 03h = x32 only 04h = single i/o spi, 3-byte address 05h = multi i/o spi, 3-byte address 29h 05h 2ah 08h max. number of bytes in multi-byte write = 2 n (00 = not supported) 2bh 00h 2ch 02h number of erase block regions within device 1 = uniform device, 2 = parameter block 2dh 1fh erase block region 1 information (refer to cfi publication 100) 2eh 00h 2fh 10h 30h 00h 31h 3dh erase block region 2 information (refer to cfi publication 100) 32h 00h 33h 00h 34h 01h 35h 00h erase block region 3 information (refer to cfi publication 100) 36h 00h 37h 00h 38h 00h 39h 00h erase block region 4 information (refer to cfi publication 100) 3ah 00h 3bh 00h 3ch 00h
34 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet note cfi data related to v cc and time-outs may differ from actual v cc and time-outs of the product. please consult the ordering information tables to obtain the v cc range for particular part numbers. please consult the ac characteristics on page 57 for typical timeout specifications. table 9.6 product group cfi primary vendor -specific extended query byte data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number, ascii 44h 33h minor version number, ascii 45h 15h address sensitive unlock (bits 1-0) 00b = required, 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0010b = 0.20 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 00h erase suspend 0 = not supported, 1 = read only, 2 = read & write 47h 01h sector protect 00 = not supported, x = number of sectors in per smallest group 48h 00h temporary sector unprotect 00 = not supported, 01 = supported 49h 05h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 4ah 00h simultaneous operation 00 = not supported, x = number of sectors outside bank 1 4bh 01h burst mode type 00 = not supported, 01 = supported 4ch 03h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 03 = 256 byte page 4dh 85h acc (acceleration) supply minimum 00 = not supported, (d7-d4: volt, d3-d0: 100 mv) 4eh 95h acc (acceleration) supply maximum 00 = not supported, (d7-d4: volt, d3-d0: 100 mv) 4fh 07h w# protection 07 = uniform device with top or bottom write protect (user select) 50h 00h program suspend 00 = not supported, 01 = supported
january 29, 2013 s25fl032p_00_09 s25fl032p 35 data sheet 9.8 read-id (read_id) the read_id instruction provides the s25fl032p manu facturer and device information and is provided as an alternative to the release from deep power-down and read electr onic signature (res), and the jedec read identification (rdid) commands. the instruction is initiated by drivi ng the cs# pin low and shifting in (via t he si input pin) the instruction code ?90h? followed by a 24-bit address (w hich is either 00000h or 00001h). following this, the manufacturer id and the device id are shifted out on the so output pin starting after the falling edge of the sck serial clock input signal. if the 24-bit address is set to 000000h, the manufacturer id is read out first followed by the device id. if the 24-bit address is set to 000001h, then the device id is read out first followed by the manufacturer id. the manufacturer id and the device id are always shifted out on the so output pin with the msb first, as shown in figure 10-14. once the device is in read-id mode, the manufacturer id and device id output data toggles betwe en address 000000h and 000001h until terminated by a low to high transition on the cs# input pin. the maximum clock frequency for the read-id (90h) command is at 104 mhz (fast_read). the manufacturer id & device id is outp ut continuously until terminated by a low to high transition on cs# chip select input pin. figure 9.10 read-id (rdid) comm and timing diagram table 9.7 read_id data-out sequence address uniform manufacturer identification 00000h 01h device identification 00001h 15h c s # s ck s i s o 0 high imped a nce 8 7 6 5 4 3 22 19 3 1 3 0 2 8 10 9 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 3 247 46 2 3 22 21 0 1 2 3 0 1 2 3 4 5 6 7 in s tr u ction 24-bit addre ss n o i t a c i f i t n e d i e c i v e d n o i t a c i f i t n e d i e r u t c a f u n a m b s m
36 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.9 write enable (wren) the write enable (wren) command (see figure 9.11 ) sets the write enable latch (wel) bit to a 1, which enables the device to accept a write status register, program, or erase command. the wel bit must be set prior to every page program (pp), quad page program (qpp), parameter sector erase (p4e, p8e), erase (se or be), write registers (wrr) and otp program (otpp) command. the host system must first drive cs# low, wr ite the wren command, and then drive cs# high. figure 9.11 write enable (wren) command sequence 9.10 write disable (wrdi) the write disable (wrdi) command (see figure 9.12 ) resets the write enable latch (wel) bit to a 0, which disables the device from acceptin g a page program (pp), quad page program (qpp), parameter sector erase (p4e, p8e), erase ( se, be), write regi sters (wrr) and otp program (otpp) command. the host system must first drive cs# low, write the wrdi command, and then drive cs# high. any of following conditions resets the wel bit: ? power-up ? write disable (wrdi) command completion ? write registers (wrr) command completion ? page program (pp) command completion ? quad page program (qpp) completion ? parameter sector erase (p4e, p8e) completion ? sector erase (se) command completion ? bulk erase (be) command completion ? otp program (otpp) completion figure 9.12 write disable (wrdi) command sequence c s # s ck s i s o hi-z comm a nd 012 3 45 67 mode 3 mode 0 0 1 2 3 4 5 6 7 comm a nd c s # hi-z s ck s i s o mode 3 mode 0
january 29, 2013 s25fl032p_00_09 s25fl032p 37 data sheet 9.11 read status register (rdsr) the read status register (rds r) command outputs the state of the status register bits. table 9.8 shows the status register bits and their functions. the rdsr command may be written at any time, even while a program, erase, or wr ite registers operat ion is in progress. the host system should check the write in progress (wip) bit before sending a new command to th e device if an operation is already in progress. figure 9.13 shows the rdsr command sequence, which also s hows that it is possibl e to read the status register continuously until cs# is driven high. the maximum clock frequency for the rdsr command is 104 mhz. figure 9.13 read status register (rdsr) command sequence the following describes the status and co ntrol bits of the status register. write in progress (wip) bit: indicates whether the device is busy pe rforming a write regi sters, program, or erase operation. this bit is read-only, and is controlled internally by the device. if wip is 1, one of these operations is in progress; if wip is 0, no such operation is in pr ogress. this bit is a read-only bit. write enable latch (wel) bit: determines whether the device will ac cept and execute a write registers, program, or erase command. when set to 1, the device accepts these commands; when set to 0, the device rejects the commands. this bit is set to 1 by wr iting the wren command, and set to 0 by the wrdi command, and is also automatically reset to 0 after t he completion of a write regi sters, program, or erase operation, and after a power down/power up sequence. we l cannot be directly set by the wrr command. table 9.8 s25fl032p status register bit status register bi t bit function description 7 srwd status register write disable 1 = protects when w#/acc is low 0 = no protection, even when w#/acc is low 6 p_err programming error occurred 0 = no error 1 = error occurred 5 e_err erase error occurred 0 = no error 1 = error occurred 4bp2 block protect protects selected block from program or erase 3bp1 2bp0 1 wel write enable latch 1 = device accepts write registers, program or erase commands 0 = ignores write registers, program or erase commands 0 wip write in progress 1 = device busy a write registers, program or erase operation is in progress 0 = ready. device is in standby mode and can accept commands. comm a nd hi-z m s b m s b s t a t us regi s ter o u t s t a t us regi s ter o u t 0 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 s o s i s ck c s # mode 3 mode 0
38 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet block protect (bp2, bp1, bp0) bits: define the portion of the memory area that will be protected against any changes to the stored data. the bloc k protection (bp2, bp1, bp0) bits are either volatile or non-volatile, depending on the state of the non-volatile bit bpnv in the configuration regi ster. the block protection (bp2, bp1, bp0) bits are written with the wr ite registers (wrr) instru ction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1?s, the relevant memory area is protected against page program (pp), parameter sector erase (p4e, p8e), sector erase (se), quad page programming (qpp) and bulk erase (be) instructions. if the hardware protec ted mode is enabled, bp2:bp0 cannot be changed. the bulk erase (be) instruction ca n be executed only when the block prot ection (bp2, bp1, bp0) bits are set to 0?s. the default condition of the bp2-0 bits is binary 000 (all 0?s). erase error bit (e_err): the erase error bit is used as a erase operation success and failure check. when the erase error bit is set to a ?1?, it indicates that there was an error which occurred in the last erase operation. with the erase error bit se t to a ?1?, this bit is reset with the clear status register (clsr) command. program error bit (p_err): the program error bit is used as a program operation success and failure check. when the program error bit is set to a ?1?, it indicates that there wa s an error which occurred in the last program operation. with the program er ror bit set to a ?1?, this bit is re set with the clear status register (clsr) command. status register write disable (srwd) bit: provides data protection when used together with the write protect (w#/acc) signal. the status register write di sable (srwd) bit is operat ed in conjunction with the write protect (w#/acc) inpu t pin. the status register write disable (srwd) bit and the write protect (w#/ acc) signal allow the device to be put in the hard ware protected mode. with the status register write disable (srwd) bit set to a ?1? and the w#/acc driven to the logic low st ate, the device ent ers the hardware protected mode; the non-volatile bits of the status register (srwd, bp2, bp1, bp0) and the nonvolatile bits of the configuration register (tbparm, tbprot, bpnv and quad) become read- only bits and the write registers (wrr) instruction opcode is no longer accepted for execution. note : the p_err and e_err bits will not be set to a 1 if the application writes to a protected memory area. 9.12 read configuration register (rcr) the read configuration regi ster (rcr) instruction opco de allows the configuration register contents to be read out of the so serial out put pin. the configuration register contents may be read at any time, even while a program, erase, or wr ite cycle is in progress. when one of these cycles is in progress, it is recommended to the user to check the write in progr ess (wip) bit of the stat us register before is suing a new instruction opcode to the device. the conf iguration register originally shows 00h when the device is first shipped from the factory to the customer. refer to section 7.8 on page 16 for more details. figure 9.14 read configuration register (rcr) instruction sequence config u r a tion regi s ter o u t n o i t c u r t s n i 1 3 0 1 29 8 7 6 5 4 0 14 1 3 12 11 15 1 3 20 7654 s ck s i s o m s b high imped a nce c s # config u r a tion regi s ter o u t m s b m s b 1 3 20 7654 7 19 1 8 17 16 20 22 21 2 3
january 29, 2013 s25fl032p_00_09 s25fl032p 39 data sheet 9.13 write registers (wrr) the write registers (wrr) command allo ws changing the bits in the stat us and configuration registers. a write enable (wren) command, which itself sets the wr ite enable latch (wel) in the status register, is required prior to writing the wrr command. table 9.8 shows the status register bits and their functions. the host system must drive cs# low, then write the wrr command and the appropriate data byte on si figure 9.15 . the wrr command cannot change the stat e of the write enable latch (bit 1). the wren command must be used for that purpose. the status register consists of one dat a byte in length; similarly, the conf iguration register is also one data byte in length. the cs# pin must be driven to the logic low state during the en tire duration of the sequence. the wrr command also controls the va lue of the status regi ster write dis able (srwd) bit. the srwd bit and w#/acc pin together place the device in the hardwa re protected mode (hpm). the device ignores all wrr commands once it enters the hardware protected mode (hpm). table 9.9 shows that w#/acc must be driven low and the srwd bit must be 1 for this to occur. the write registers (wrr) instruction has no effect on the p/e er ror and the wip bits of the status & configuration registers. any bit reserved for the future is always read as a ?0? the cs# chip select input pin must be driven to the logic high state after the eighth (see figure 9.15 ) or sixteenth (see figure 9.16 ) bit of data has been latched in. if not, th e write registers (wrr) instruction is not executed. if cs# is driven high after the eighth cycle then only the status register is written to; otherwise, after the sixteenth cycle both the stat us and configuration regi sters are written to. as soon as the cs# chip select input pin is driven to the logi c high state, the self-timed write regi sters cycle is initiated. while the write registers cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is a ?1? during the self-timed writ e registers cycle, and is a ?0? when it is completed. when the write registers c ycle is completed, the write enable latch (wel) is set to a ?0?. the wrr command can operate at a maximum clock frequency of 104 mhz. figure 9.15 write registers (wrr) instruction sequence ? 8 data bits n i r e t s i g e r s u t a t s n o i t c u r t s n i 1 3 0 1 29 8 7 6 5 4 0 14 1 3 12 11 15 1 3 20 7654 s ck s i s o m s b high imped a nce c s #
40 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet figure 9.16 write registers (wrr) instru ction sequence ? 16 data bits note as defined by the values in the block protect (bp2, bp 1, bp0) bits of the status register, as shown in table 7.3 on page 18 . table 9.9 shows that neither w#/acc or srwd bit by themselves can enable hpm. the device can enter hpm either by setting the srwd bi t after driving w#/acc low, or by driving w#/acc low after setting the srwd bit. however, the device disables hpm only when w#/acc is driven high. note that hpm only protects against changes to the status register. since bp2 :bp0 cannot be changed in hpm, the size of t he protected area of the memory array cannot be changed. note that hpm provides no protection to the memory array area outside that spec ified by bp2:bp0 (software protected mode, or spm). if w#/acc is permanently tied high, hpm can never be activated, and onl y the spm (bp2:bp0 bits of the status register) can be used. the status and configuration registers originally defaul t to 00h, when the device is first shipped from the factory to the customer. note : hpm is disabled when the quad i/o mode is enabl ed (quad bit = 1 in the c onfiguration register). w# becomes io2; therefore, hpm cannot be utilized. table 9.9 protection modes w#/ acc srwd bit mode write protection of registers memory content protected area unprotected area 11 software protected (spm) status & configuration registers are writable (if wren instruction has set the wel bit). the values in the srwd, bp2, bp1, & bp0 bits & those in the configuration register can be changed protected against page program, parameter sector erase, sector erase, and bulk erase ready to accept page program, parameter sector erase, & sector erase instructions 10 00 01 hardware protected (hpm) status & configuration registers are hardware write protected. the values in the srwd, bp2, bp1, & bp0 bits & those in the configuration register cannot be changed protected against page program, parameter sector erase, sector erase, and bulk erase ready to accept page program, parameter sector erase, sector erase instructions i i n s t r u c t i o n s t a t u s r e g i s t e r i n 1 3 2 1 0 9 8 7 6 5 4 0 1 4 1 3 1 2 1 1 1 5 1 3 2 0 7 6 5 4 s c k s i s o m s b h i g h i m p e d a n c e c s s # c o n f i g u r a t i o n r e g i s t e r i n 1 8 1 7 1 6 2 2 2 1 2 0 1 9 2 3 1 3 2 0 7 6 5 4 m s b
january 29, 2013 s25fl032p_00_09 s25fl032p 41 data sheet 9.14 page program (pp) the page program (pp) command changes specified bytes in the memory array (from 1 to 0 only). a wren command is required prior to writing the pp command. the host system must drive cs# low, and then write the pp command, three addre ss bytes, and at least one data byte on si. if the 8 least significant address bits (a 7-a0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are prog rammed from the starting add ress of the same page (from the address whose 8 least signific ant bits are all zero). cs# must be driven low for the entire duration of the pp sequence. the command sequence is shown in figure 9.17 and table 9.1 on page 23 . the device programs only the last 256 data bytes sent to the device. if the 8 least significant address bits (a7- a0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are programmed from the starting address of the same page (from the address w hose 8 least significant bits are all zero). if fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effect on the other bytes in the same page. the host system must drive cs# high after the device has latched the 8th bit of the data byte, otherwise the device does not execute the pp command. the pp operat ion begins as soon as cs# is driven high. the device internally controls the timing of the operation, which r equires a period of t pp . the status register may be read to check the value of the writ e in progress (wip) bit while the pp operation is in progress. the wip bit is 1 during the pp operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before th e operation completes (the exact timing is not specified). the device does not execute a page program (pp) command that specifies a page that is protected by the block protect bits (bp2:bp0) (see table 7.3 on page 18 ). figure 9.17 page program (pp) command sequence 0 3 4 33 3 2 3 1 3 0 29 2 8 10 9 8 7 6 5 4 3 2 1 3 5 3 6 3 7 38 3 9 46 45 44 4 3 42 41 40 47 4 8 49 50 51 52 5 3 54 55 207 3 2072 2076 2075 2074 2079 207 8 2077 2 3 22 21 3 21 07 6 5 4 3 2 1 0 d a t a byte 1 24 bit addre ss comm a nd d a t a byte 2 d a t a byte 3 d a t a byte 256 m s b m s b m s b m s b m s b s ck s i s ck s i 7 65 4 3 2 1 0 76 54 3 21 0 7 6 5 4 3 210 c s # c s # mode 0 mode 3
42 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.15 quad page program (qpp) the quad page program instruction is similar to the page program instru ction, except that the quad page program (qpp) instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io0 (si), io1 (so) , io2 (w#/acc), and io3 (hold# ), instead of just one pin (si) as in the case of the page program (pp) instruction. this effectively increases the data transfer rate by up to four times, as compared to the page prog ram (pp) instruction. the qpp feature can improve performance for prom programmer and applications that have slow cloc k speeds < 5 mhz. systems with faster clock speed will not realize much benefit for th e qpp instruction since the inherent page program time is much greater than the time it take to clock-in the data. to use qpp, the quad enable bit in the configurati on register must be set (q uad = 1). a write enable instruction must be executed before the device will accept the quad page program instruction (status register-1, wel = 1). the inst ruction is initiated by driving the cs# pin low then shifting t he instruction code ?32h? followed by a 24 bit address (a23-a0) and at least one data byte, into the io pins. the cs# pin must be held low for the entire length of the instruction whil e data is being sent to the de vice. all other functions of quad input page program are identic al to standard page program. the q pp instruction sequence is shown below. figure 9.18 quad page program instruction sequence *msb c s # s ck s o/io1 in s tr u ction 24 bit addre ss byte 2 3 9 2 3 * 5 s i/io0 01 4567 8 9 byte 1 6 7 * 4 w#/acc/io2 hold#/io 3 22 21 7 * 3 7 * 3 6 2 6 2 5 1 5 1 4 0 4 0 10 c s # s ck s o/io1 s i/io0 w#/acc/io2 hold#/io 3 2 3 2 8 29 3 2 33 3 4 3 5 3 6 3 7 38 3 0 3 1 byte 4 byte 3 3 2 1 0 5 6 7 * 4 3 2 1 0 3 2 1 0 51 40 41 44 45 46 47 4 8 49 50 42 4 3 54 55 52 5 3 5 3 6 5 3 7 5 38 5 3 9 540 541 542 54 3 byte 6 byte 5 byte 8 byte 7 byte 10 byte 9 byte 12 byte 11 byte 254 byte 25 3 byte 256 byte 255 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0 7 * 3 6 2 5 1 4 0
january 29, 2013 s25fl032p_00_09 s25fl032p 43 data sheet 9.16 parameter sector erase (p4e, p8e) the parameter sector erase (p4e, p8e) command sets all bits at all addresses within a specified sector to a logic 1 (ffh). a wren command is required prior to wr iting the parameter se ctor erase commands. the host system must drive cs# low, and then write the p4e or p8e comm and, plus three address bytes on si. any address within the sector (see table 8.1 on page 20 and table 8.2 on page 21 ) is a valid address for the p4e or p8e command. cs# must be driven low fo r the entire durat ion of the p4e/p8e sequence. the command sequence is shown in figure 9.19 and table 9.1 on page 23 . the host system must drive cs# high after the devic e has latched the 24th bit of the p4e/p8e address, otherwise the device does not exec ute the command. the parameter sect or erase operation begins as soon as cs# is driven high. the device internally controls th e timing of the operation, which requires a period of t se . the status register may be read to check the value of the write in progress (wip) bit while the parameter sector erase oper ation is in progress. the wip bit is 1 during the p4e/p8e operation, and is 0 when the operation is completed. the device internal ly resets the write enable latch to 0 before the operation completes (the exact timing is not specified). a parameter sector erase (p4e, p8e) instruction applied to a sector th at has been write protected through the block protect bits will not be executed. the parameter sector erase command (p8e) erases two of the 4 kb sectors in selected address space. the parameter sector erase command (p8e) erases two sequential 4 kb parameter sectors in the selected address space. the address lsb is disregarded so that two sequential 4 kb parameter sectors are erased. the 24 bit address is any location within the first sector to be erased (n), and the next sequential 4 kb parameter sector will also be erased (n+1). the 4 kb parameter sector will only be erased properly if n or n+1 is a valid 4 kb parameter sector. i.e. if n is not a va lid 4k parameter sector, then it will not be erased. if n+1 is not a valid 4 kb parameter se ctor, then it will not be erased. figure 9.19 parameter sector erase (p4e, p8e) instruction sequence 1 3 0 1 29 8 7 6 5 4 0 3 1 3 0 29 2 8 in s tr u ction 24 bit addre ss 2 3 21 22 1 3 20 s ck s i m s b c s # 20h or 40h
44 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.17 sector erase (se) the sector erase (se) command sets all bits at all addr esses within a specified sect or to a logic 1. a wren command is required prior to writing the se command. the host system must drive cs# lo w, and then write the se command plus three address bytes on si. any address within the sector (see table 7.3 on page 18 ) is a valid address for the se command. cs# must be driven low for the entire duration of the se s equence. the command sequence is shown in figure 9.20 and table 9.1 on page 23 . the host system must drive cs# high after the device has latched the 24th bit of the se address, otherwise the device does not execute the command. the se operat ion begins as soon as cs# is driven high. the device internally controls the timing of the operation, which r equires a period of t se . the status register may be read to check the value of the writ e in progress (wip) bit while the se operation is in progress. the wip bit is 1 during the se operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before th e operation completes (the exact timing is not specified). the device only executes a se command if all block protect bits (bp2:bp0) are 0 (see table 7.3 on page 18 ). otherwise, the devi ce ignores the command. figure 9.20 sector erase (se) command sequence c s # s ck s i s o m s b comm a nd 24 b it addre ss 01 2 3 45 67 8 910 2 8 29 3 0 3 1 2 3 22 21 3 2 1 0 hi-z mode 0 mode 3
january 29, 2013 s25fl032p_00_09 s25fl032p 45 data sheet 9.18 bulk erase (be) the bulk erase (be) command sets all the bits within the entire memory array to logic 1s. a wren command is required prior to writing the be command. the host system must drive cs# lo w, and then write the be command on si. cs# must be driven low for the entire duration of the be sequence. t he command sequence is shown in figure 9.21 and table 9.1 on page 23 . the host system must drive cs# high after the device has latched the 8th bit of the ce command, otherwise the device does not execute the command. the be operat ion begins as soon as cs# is driven high. the device internally controls the timing of the operation, which r equires a period of t be . the status register may be read to check the value of the writ e in progress (wip) bit while the be operation is in progress. the wip bit is 1 during the be operation, and is 0 when the operation is completed. the device internally resets the write enable latch to 0 before th e operation completes (the exact timing is not specified). the device only executes a be command if all block protect bits (bp2:bp0) are 0 (see table 7.3 on page 18 ). otherwise, the devi ce ignores the command. figure 9.21 bulk erase (be) command sequence 01 2 4 56 7 comm a nd c s # s ck s i 3 s o hi-z mode 0 mode 3
46 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.19 deep power-down (dp) the deep power-down (dp) command provides the lowe st power consumption mode of the device. it is intended for periods when the device is not in active use, and ignores all commands except for the release from deep power-down (res) command. the dp mode therefore provides the maximum data protection against unintended write operations. the standard standby mode, which the device goes into automatically when cs# is high (and all operations in progress ar e complete), should generally be used for the lowest power consumption when the quickest retu rn to device activity is required. the host system must drive cs# low, and then write the dp command on si. cs# must be driven low for the entire duration of the dp sequence. the command sequence is shown in figure 9.22 and table 9.1 on page 23 . the host system must drive cs# high after the device has latched the 8th bit of the dp command, otherwise the device does not execute the command. after a delay of t dp, the device enters the dp mode and current reduces from i sb to i dp (see table 16.1 on page 56 ). once the device has entered the dp mode, all commands are ignored except the res command (which releases the device from the dp mode). the res comm and also provides the elec tronic signature of the device to be output on so, if desired (see section 9.20 and 9.20.1) . dp mode automatically terminates when power is re moved, and the device alwa ys powers up in the standard standby mode. the device rejects any dp command issued while it is executing a pr ogram, erase, or write registers operation, and continues the oper ation uninterrupted. figure 9.22 deep power-down (dp) command sequence c s # s ck s i s o s t a nd b y mode deep power-down mode comm a nd 0 1 2 3 4567 t dp hi-z mode 0 mode 3
january 29, 2013 s25fl032p_00_09 s25fl032p 47 data sheet 9.20 release from deep power-down (res) the device requires the release from deep power-do wn (res) command to exit the deep power-down mode. when the device is in the deep power-d own mode, all commands except res are ignored. the host system must drive cs# low and write the res command to si. cs# mu st be driven low for the entire duration of the sequence. the command sequence is shown in figure 9.23 and table 9.1 on page 23 . the host system must drive cs# high t res(max) after the 8-bit res command byte. the device transitions from dp mode to the standby mode after a delay of t res (see figure 18.1 ). in the standby mode, the device can execute any read or write command. note : the res command does not reset the write enable latch (wel) bit. figure 9.23 release from deep power-down (res) command sequence c s # s ck s i s o 0 1 2 3 4 5 6 7 comm a nd deep power-down mode t re s s t a nd b y mode mode 0 hi-z mode 3
48 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 9.20.1 release from deep power-down and read electronic signature (res) the device features an 8-bit elec tronic signature, which can be r ead using the res command. see figure 9.24 and table 9.1 on page 23 for the command sequence and signat ure value. the electronic signature is not to be confused wi th the identification dat a obtained using the rdid command. the device offers the electronic signature so that it can be used with previous devices that offered it; however, the electronic signature should not be used for new designs, which should read the rdid data instead. after the host system drives cs# low, it must write the res command followed by 3 dummy bytes to si (each bit is latched on si during the rising edge of sck). t he electronic signature is then output on so; each bit is shifted out on the falling edge of sck. the res operation is terminated by driving cs# high after the electronic signature is read at leas t once. additional clock cycles on sck with cs# low cause the device to output the electronic si gnature repeatedly. when cs# is driven high, the device transitions from dp mode to the standby mode after a delay of t res , as previously described. the res command always provides access to the electronic signature of the device and can be applied even if dp mode has not been entered. any res command issued while an erase, program, or writ e registers operation is in progress not executed, and the operation contin ues uninterrupted. figure 9.24 release from deep power-down and res command sequence 9.21 clear status register (clsr) the clear status register command resets bit sr5 (erase fail flag) and bit sr6 (pr ogram fail flag). it is not necessary to set the wel bit befor e the clear sr fail flags command is executed. the wel bit will be unchanged after this command is executed. this command also resets the state machine and loads latches figure 9.25 clear status register (c lsr) instruction sequence c s # s ck s i s o 3 d u mmy byte s hi-z m s b deep power-down mode s t a nd b y mode 0 1 2 3 4567 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 electronic id comm a nd t re s 2 3 22 21 3 2 10 7 65 4 3 2 1 0 m s b 3 9 3 2 7 6 5 4 0 i n s t r u c t i o n s c k s i 1 c s s #
january 29, 2013 s25fl032p_00_09 s25fl032p 49 data sheet 9.22 otp program (otpp) the otp program command programs data in the otp region, which is in a different address space from the main array data. refer to, otp regions on page 50 for details on the otp regi on. the protocol of the otp program command is the same as the page progra m command, except that the otp program command requires exac tly one byte of data; ot herwise, the command will be ignore d. to program the otp in bit granularity, the rest of the bits within the data byte can be set to ?1?. the otp memory space can be programmed one or more times, provided that the otp memory space is not locked (as described in ?locking ot p regions?). subsequent otp progra mming can be performed only on the unprogrammed bits (that is, ?1? data). note: the write enable (wren) command must pr ecede the otpp command before programming of the otp can occur. figure 9.26 otp program instruction sequence 9.23 read otp data bytes (otpr) the read otp data bytes command reads data from the otp region. refer to ? otp regions ? for details on the otp region. the protocol of the read otp data bytes command is the same as the fast read data bytes command except t hat it will not wrap to the starting addres s after the otp address is at its maximum; instead, the data wi ll be indeterminate. figure 9.27 read otp instruction sequence 1 3 2 1 0 9 8 7 6 5 4 0 3 1 3 0 2 9 2 8 i n s t r u c t i o n 2 4 b i t a d d r e s s 2 3 2 1 2 2 1 3 2 0 3 6 3 5 3 4 3 3 3 2 3 9 3 8 3 7 1 3 2 0 7 6 5 4 d a t a b y t e 1 s c k s i m s b m s b c s # 1 30 1 29 8 7 6 5 41 3 030 29 28 instruction 24 bit address 23 21 22 1 32 0 1 32 0 7654 36 35 34 33 9 3 2 338 37 1 32 0 7654 dummy byte 44 43 42 41 7 4 0 446 45 data out 1 data out 2 sck si so msb high impedance 7 msb cs
50 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 10. otp regions the otp regions are separately addressable from the main array and consists of tw o 8-byte (esn), thirty 16-byte, and one 10-byte regions that can be individually locked. ? the two 8-byte esn region is a special order part (ple ase contact your local spansion sales representative for further details). the two 8-byte regions enabl e permanent part identification through an electronic serial number (esn). the customer can utilize the esn to pair a flash device with the system cpu/asic to prevent system cloning. the span sion factory programs and locks th e lower 8-byte esn with a 64-bit randomly generated, unique number. the upper 8-byte esn is left blank for customer use or, if special ordered, spansion can program (and lock) in a unique customer id. ? the thirty 16-byte and one 10-byte otp regions are open for the customer usage. ? the thirty 16-byte, one 10-byte, and upper 8-byte esn otp regions can be individually locked by the end user. once locked, the data cannot changed. the locking process is permanent and cannot be undone. the following general conditions should be noted with respect to the otp regions: ? on power-up, or following a hardware reset, or at the end of an otpp or an otpr command, the device reverts to sending commands to the normal address space. ? reads or programs outside of the otp regions will be ignored ? the otp region is not accessible when the de vice is executing an embedded program or embedded erase algorithm. ? the acc function is not available when accessing the otp regions. ? the thirty 16-byte and one 10-byte otp regions are le ft open for customer usage, but special care of the otp locking must be maintained, or else a malevolent user can permanently lock the otp regions. this is not a concern, if the ot p regions are not used. 10.1 programming otp address space the protocol of the otp program command (42h) is the same as the page program command. refer to table 9.1 for the command description and protocol. the ot p program command can be issued multiple times to any given otp address, but this address sp ace can never be erased. after a given otp region is programmed, it can be locked to prevent further programmi ng with the otp lock registers (refer to section 10.3 ). the valid address range for otp program is depicted in the figu re below. otp program operations outside the valid ot p address range will be ignored. 10.2 reading otp data the protocol of the otp read command (4bh) is the same as that of the fast read command. refer to table 9.1 for the command description and protocol. the vali d address range for otp reads is depicted in the figure below. otp read operations outs ide the valid otp addr ess range will yield indeterminate data. 10.3 locking otp regions in order to permanently lock the esn and otp regions, individual bits at the specified addresses can be set to lock specific regions of otp memory, as highlighted in figures 10.1 and 10.2 . table 10.1 esn1 and esn2 lock register esn1 (bit 0) lock register esn2 (b it 1) esn1 region contains esn2 region contains standard part 1h 1h 0h 0h special order part 1h 1h/0h unique random pattern factory/customer programmed pattern
january 29, 2013 s25fl032p_00_09 s25fl032p 51 data sheet figure 10.1 otp memory map - part 1 notes 1. bit 0 at address 0x100h locks esn1 region. 2. bit 1 at address 0x100h locks esn2 region. 3. bits 2-7 (?x?) are not programmable and will be ignored. addre ss otp region 0x21 3 h 0x204h 0x20 3 h 0x1f4h 0x1f 3 h 0x1e4h 0x1e 3 0x1d4h 0x1d 3 h 0x1c4h 0x1c 3 h 0x1b4h 0x1b 3 h 0x1a4h 0x1a 3 h 0x194h 0x19 3 h 0x1 8 4h 0x1 83 h 0x174h 0x17 3 h 0x164h 0x16 3 h 0x154h 0x15 3 h 0x144h addre ss bit lock s region? 0x14 3 h 0otp1 1otp2 0x1 3 4h 2otp 3 0x1 33 h 3 otp4 4otp5 0x124h 5otp6 0x12 3 h 6otp7 7otp 8 0x114h 0otp9 0x11 3 h 1otp10 0x112h 2otp11 0x111h 3 otp12 4otp1 3 0x10ah 5otp14 0x109h 6otp15 7otp16 0x102h 0e s n1 0x101h re s erved 1e s n2 0x100h 2 - 7 r e s erved 16 b yte s (otp15) 16 b yte s (otp14) 16 b yte s (otp1 3 ) 16 b yte s (otp12) 16 b yte s (otp5) 16 b yte s (otp11) 16 b yte s (otp10) 16 b yte s (otp9) 16 b yte s (otp6) 16 b yte s (otp7) 16 b yte s (otp 8 ) 0x100h 0x112h 0x11 3 h 16 b yte s (otp16) 8 b yte s (e s n1) 8 b yte s (e s n2) 16 b yte s (otp1) 16 b yte s (otp2) 16 b yte s (otp 3 ) 16 b yte s (otp4) x x x x x x bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
52 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet figure 10.2 otp memory map - part 2 note 1. bit 7 (?x?) at address 0x215h is not programmable and will be ignored. addre ss otp region 0x2ffh 0x2f6h 0x2f5h 0x2e6h 0x2e5 0x2d6h 0x2d5h 0x2c6h 0x2c5h 0x2b6h 0x2b5h 0x2a6h 0x2a5h 0x296h 0x295h 0x2 8 6h 0x2 8 5h 0x276h 0x275h 0x266h 0x265h addre ss b it lock s region? 0otp17 0x256h 1otp1 8 0x255h 2otp19 3 otp20 0x246h 4otp21 0x245h 5otp22 6otp2 3 0x2 3 6h 7otp24 0x2 3 5h 0otp25 1otp26 0x226h 2otp27 0x225h 3 otp2 8 4otp29 0x216h 5otp 3 0 0x215h 6 otp 3 1 0x214h 7 re s erved 16 b yte s (otp21) 0x214h 0x215h 16 b yte s (otp17) 16 b yte s (otp1 8 ) 16 b yte s (otp19) 16 b yte s (otp20) 16 b yte s (otp27) 16 b yte s (otp26) 16 b yte s (otp25) 16 b yte s (otp22) 16 b yte s (otp2 3 ) 16 b yte s (otp24) 10 b yte s (otp 3 1) 16 b yte s (otp 3 0) 16 b yte s (otp29) 16 b yte s (otp2 8 ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
january 29, 2013 s25fl032p_00_09 s25fl032p 53 data sheet 11. power-up and power-down during power-up and power-down, certain conditions must be observed. cs# mu st follow the voltage applied on v cc , and must not be driven low to select the device until v cc reaches the allowable values as follows (see figure 11.1 and table 11.1 on page 54 ): ? at power-up, v cc (min.) plus a period of t pu ? at power-down, gnd a pull-up resistor on chip select (cs#) typically meets proper power-up and power-down requirements. no read, write registers, program, or erase command should be sent to the device until v cc rises to the v cc min., plus a delay of t pu . at power-up, the device is in standby mode (not deep power-down mode) and the wel bit is reset (0). each device in the host system should have the v cc rail decoupled by a suitabl e capacitor close to the package pins (this c apacitor is generally of the order of 0.1 f), as a precaution to stabilizing the v cc feed. when v cc drops from the operating vo ltage to below the minimum v cc threshold at power-down, all operations are disabled and the device does not respond to any comma nds. note that da ta corruption may result if a power-down occurs while a write regi sters, program, or erase operation is in progress. figure 11.1 power-up timing diagram figure 11.2 power-down and voltage drop v cc v cc (max) v cc (min) full device access t pu time vcc v cc (m a x) v cc (min) v cc (c u t-off) v cc (low) t pd t pu device acce ss allowed no device acce ss allowed time
54 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 12. initial delivery state the device is delivered with the memory array erased i. e. all bits are set to 1 (ffh) upon initial factory shipment. the status register and configuration re gister contains 00h (all bits are set to 0). 13. program acceleration via w#/acc pin the program acceleration func tion requires applying v hh to the w#/acc input, and then waiting a period of t wc . minimum t vhh rise and fall times is required for w#/acc to change to v hh from v il or v ih . removing v hh from the w#/acc pin returns the device to normal operation after a period of t wc . figure 13.1 acc program acceleration timing requirements note only read status register (rdsr) and page program (pp) operation are allow when acc is at (v hh ). the w#/acc pin is disabled during quad i/o mode. table 11.1 power-up / power-down voltage and timing symbol parameter min max unit v cc(min) v cc (minimum operation voltage) 2.7 v v cc (cut-off) v cc (cut off where re-initialization is needed) 2.4 v v cc (low) v cc (low voltage for initialization to occur at read/standby) v cc (low voltage for initialization to occur at embedded) 0.2 2.3 v t pu v cc (min.) to device operation 300 s t pd v cc (low duration time) 1.0 s table 13.1 acc program accelera tion specifications symbol parameter min. max unit v hh a cc pin voltage high 8.5 9.5 v t vhh a cc voltage rise and fall time 2.2 s t wc acc at v hh and v il or v ih to first command 5 s acc comm a nd ok v hh v il or v ih t vhh t wc t wc t vhh v il or v ih
january 29, 2013 s25fl032p_00_09 s25fl032p 55 data sheet 14. electrical specifications 14.1 absolute maximum ratings notes 1. minimum dc voltage on input or i/os is - 0.5v. during voltage transitions, inputs or i/os may undershoot gnd to - 2.0v for periods of up to 20 ns. see figure 14.1 . maximum dc voltage on input or i/os is v cc + 0.5v. during voltage transitions inputs or i/os may overshoot to v cc + 2.0v for periods up to 20 ns. see figure 14.2 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditi ons above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditi ons for extended periods may affect device reliability. figure 14.1 maximum negative overshoot waveform figure 14.2 maximum positive overshoot waveform 15. operating ranges note operating ranges define those limits between which functionality of the device is guaranteed. description rating ambient storage temperature -65c to +150c voltage with respect to ground: all inputs and i/os -0.5v to v cc +0.5v output short circuit current (note 2) 200 ma 20 ns 20 ns +0.8v ?0.5v 20 ns ?2.0v 20 ns 20 ns v cc +2.0v v cc +0.5v 20 ns 2.0v table 15.1 operating ranges description rating ambient operating temperature (t a ) industrial ?40c to +85c automotive in-cabin ?40c to +105c positive power supply voltage range 2.7v to 3.6v
56 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 16. dc characteristics this section summarizes the dc characteristics of t he device. designers should check that the operating conditions in their circuit match the measurement c onditions specified in the test specifications in table 17.1 on page 57 , when relying on the quoted parameters. table 16.1 dc characteristics (cmos compatible) symbol parameter test conditions limits unit min. typ * max v cc supply voltage 2.7 3.6 v v hh acc program acceleration voltage v cc = 2.7v to 3.6v 8.5 9.5 v v il input low voltage ** -0.3 0.3 x v cc v v ih input high voltage ** 0.7 x v cc v cc +0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min. 0.4 v v oh output high voltage i oh = -0.1 ma v cc -0.6 v i li input leakage current v cc = v cc max, v in = v cc or gnd 2a i lo output leakage current v cc = v cc max, v in = v cc or gnd 2a i cc1 active power supply current - read (so = open) at 80 mhz (dual or quad) 38 ma at 104 mhz (serial) 25 at 40 mhz (serial) 12 i cc2 active power supply current (page program) cs# = v cc 26 ma i cc3 active power supply current (wrr) cs# = v cc 15 ma i cc4 active power supply current (se) cs# = v cc 26 ma i cc5 active power supply current (be) cs# = v cc 26 ma i sb1 standby current cs# = v cc ; so + v in = gnd or v cc 80 200 a i pd deep power-down current cs# = v cc ; so + v in = gnd or v cc 310 a * typical values are at t ai = 25c and v cc = 3v
january 29, 2013 s25fl032p_00_09 s25fl032p 57 data sheet 17. test conditions figure 17.1 ac measurements i/o waveform 18. ac characteristics table 17.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0. 8 v cc 0.2 v cc 0.7 v cc 0. 3 v cc inp u t level s inp u t a nd o u tp u t timing reference level s 0.5 v cc figure 18.1 ac characteristics (sheet 1 of 2) symbol (notes) parameter (notes) min. (notes) typ (notes) max (notes) unit f r sck clock frequency for read command dc 40 mhz sck clock frequency for rdid command dc 50 f c sck clock frequency for all others: fast_read, pp, qpp, p4e, p8e, se, be, dp, res, wren, wrdi, rdsr, wrr, read_id dc 104 (serial) 80 (dual/quad) mhz t wh , t ch clock high time (5) 4.5 ns t wl , t cl clock low time (5) 4.5 ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs cs# high time (read instructions) cs# high time (program/erase) 10 50 ns t css cs# active setup time (relative to sck) 3ns t csh cs# active hold time (relative to sck) 3ns t su:dat data in setup time 3 ns t hd:dat data in hold time 2 ns t v clock low to output valid 0 8 (serial) 9.5 (dual/quad) 6.5 (serial) 8 (dual/quad) 7 (dual/quad) ns t ho output hold time 2 ns t dis output disable time 8ns t hlch hold# active setup time (relative to sck) 3ns t chhh hold# active hold time (relative to sck) 3ns t hhch hold# non active setup time (relative to sck) 3ns
58 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet notes 1. typical program and erase times assume the following conditions: 25c, vcc = 3.0v; 10,000 cycles; checkerboard data pattern. 2. under worst-case conditions of 85c; v cc = 2.7v; 100,000 cycles. 3. acceleration mode (9v acc) only in program mode, not erase. 4. only applicable as a constraint for wrr instruction when srwd is set to a ?1?. 5. t wh + t wl must be less than or equal to 1/f c . 6. full vcc range (2.7 ? 3.6v) & cl = 30 pf 7. regulated vcc range (3.0 ? 3.6v) & cl = 30 pf 8. regulated vcc range (3.0 ? 3.6v) & cl = 15 pf 18.1 capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. 3. for more information on pin capacitance, please consult the ibis models. t chhl hold# non active hold time (relative to sck) 3ns t hz hold# enable to output invalid 8 ns t lz hold# disable to output valid 8 ns t wps w#/acc setup time (4) 20 ns t wph w#/acc hold time (4) 100 ns t w wrr cycle time 50 ms t pp page programming (1)(2) 1.5 3 ms t ep page programming (acc = 9v) (1)(2)(3) 1.2 2.4 ms t se sector erase time (64 kb) (1)(2) 0.5 2 sec t pe parameter sector erase time (1)(2) (4 kb or 8 kb) 200 800 ms t be bulk erase time (1)(2) 32 64 sec t res deep power-down to standby mode 30 s t dp time to enter deep power-down mode 10 s t vhh acc voltage rise and fall time 2.2 s t wc acc at vhh and vil or vih to first command 5 s figure 18.1 ac characteristics (sheet 2 of 2) symbol (notes) parameter (notes) min. (notes) typ (notes) max (notes) unit symbol parameter test conditions min typ max unit c in input capacitance (applies to sck, po7-po0, si, cs#) v out = 0v 9.0 12.0 pf c out output capacitance (applies to po7-po0, so) v in = 0v 12.0 16.0 pf
january 29, 2013 s25fl032p_00_09 s25fl032p 59 data sheet figure 18.2 spi mode 0 (0,0) input timing figure 18.3 spi mode 0 (0,0) output timing figure 18.4 hold# timing c s # s ck s i s o t c s h t c ss t c s h t c ss t crt t cft m s b in l s b in hi-z t s u:dat t hd:dat t c s c s # s ck s o l s b out t wh t wl t di s t v t ho t v t ho t chhl t hz t chhh t hlch t hhch t lz c s # s ck s o s i hold#
60 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet figure 18.5 write protect setup and hold ti ming during wrr when srwd = 1 w# c s # s ck s i s o hi-z t wp s t wph
january 29, 2013 s25fl032p_00_09 s25fl032p 61 data sheet 19. physical dimensions 19.1 soc008 wide ? 8-pin plas tic small outline package (208-mils body width) 3 602 \ 16-0 38 .0 3 \ 9.1.6 note s : 1. all dimen s ion s are in both inche s and millmeter s . 2. dimen s ioning and tolerancing per a s me y14.5m - 1994. 3 . dimen s ion d doe s not include mold fla s h, protru s ion s or gate burr s . mold fla s h, protru s ion s or gate burr s s hall not exceed 0.15 mm per end. dimen s ion e1 doe s not include interlead fla s h or protru s ion interlead fla s h or protru s ion s hall not exceed 0.25 mm per s ide. d and e1 dimen s ion s are determined at datum h. 4. the package top may be s maller than the package bottom. dimen s ion s d and e1 are determined at the outmo s t extreme s of the pla s tic body exclu s ive of mold fla s h, tie bar burr s , gate burr s and interlead fla s h. but including any mi s match between the top and bottom of the pla s tic body. 5. datum s a and b to be determined at datum h. 6. "n" i s the maximum number of terminal po s ition s for the s pecified package length. 7. the dimen s ion s apply to the flat s ection of the lead between 0.10 to 0.25 mm from the lead tip. 8 . dimen s ion " b " doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.10 mm total in exce ss of the " b " dimen s ion at maximum material condition. the dambar cannot be located on the lower radiu s of the lead foot. 9. thi s chamfer feature i s optional. if it i s not pre s ent, then a pin 1 identifier mu s t be located within the index area indicated. 10. lead coplanarity s hall be within 0.10 mm a s mea s ured from the s eating plane. package s oc 00 8 (inche s ) s oc 00 8 (mm) jedec s ymbol min max min max a 0.069 0.0 8 5 1.75 3 2.159 a1 0.002 0.009 8 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0. 3 56 0.4 83 b 10.01 3 0.01 8 0. 33 0 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.00 8 0.152 0.20 3 d 0.20 8 b s c 5.2 83 b s c e 0. 3 15 b s c 8 .001 b s c e1 0.20 8 b s c 5.2 83 b s c e .050 b s c 1.27 b s c l 0.020 0.0 3 0 0.50 8 0.762 l1 .049 ref 1.25 ref l2 .010 b s c 0.25 b s c n 8 8 0? 8 ?0? 8 ? 1 5? 15? 5? 15? 2 0? 0?
62 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 19.2 so3 016 ? 16-pin wide plastic small outline package (300-mil body width)
january 29, 2013 s25fl032p_00_09 s25fl032p 63 data sheet 19.3 une008 ? uson 8-contact (5 x 6 mm) no-lead package g1017 \ 16-038.30 \ 07.21.11 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should nt be measured in that radius area. 5 nd refer to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burrs is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. symbol min nom max note e 1.27 bsc. n 8 3 nd 4 5 l 0.55 0.60 0.65 b 0.35 0.40 0.45 4 d2 3.90 4.00 4.10 e2 3.30 3.40 3.50 d 5.00 bsc e 6.00 bsc a 0.45 0.50 0.55 a1 0.00 0.02 0.05 k 0.20 min. package une008
64 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 19.4 wnf008 ? wson 8-contact (6 x 8 mm) no-lead package g1015 \ 16-038.30 \ 07.21.11 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should nt be measured in that radius area. 5 nd refer to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burrs is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10 a maximum 0.15mm pull back (l1) may be present. symbol min nom max note e 1.27 bsc. n 8 3 nd 4 5 l 0.45 0.50 0.55 b 0.35 0.40 0.45 4 d2 4.70 4.80 4.90 e2 5.70 5.80 5.90 d 6.00 bsc e 8.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 k 0.20 min. l1 0.00 --- 0.15 10 package wnf008
january 29, 2013 s25fl032p_00_09 s25fl032p 65 data sheet 19.5 fab024 ? 24-ball ball grid array (6 x 8 mm) package
66 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet 19.6 fac024 ? 24-ball ball grid array (6 x 8 mm) package package fac024 jedec n/a d x e 8.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.20 profile a1 0.25 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 5.00 bsc. matrix footprint e1 3.00 bsc. matrix footprint md 6 matrix size d direction me 4 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter e 1.00 bsc. ball pitchl sd/ se 0.5/0.5 solder ball placement depopulated solder balls j package outline type 3642 f16-038.9 \ 09.10.09 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
january 29, 2013 s25fl032p_00_09 s25fl032p 67 data sheet 20. revision history section description revision 01 (june 9, 2008) initial release revision 02 (february 12, 2009) connection diagrams added uson package valid combinations table added tray packing type configuration register added otp description for bpnv bit configuration register table corrected tbparm description added ?default? setting information upon initial factory shipment instruction set separated mode bit and dummy bytes product group cfi primary vendor-specific extended query corrected data of 45h bytes read-id (read_id) removed statement of 8-cycle buffer for manufacturer id and the device id read status register corrected description for srwd bit in the status register table modified e_err and p_err descriptions read configuration register updated figure parameter sector erase (p4e, p8e) updated figure release from deep power-down and read electronic signature (res) updated figure otp regions modified description for the acc function power-up and power-down changed specification for t pu absolute maximum ratings corrected the table dc characteristics changed maximum specifications for i cc1 and i cc3 modified test conditions for i sb1 and i pd ac characteristics changed maximum specifications for t w added note for max values assume 100k cycles changed clock high/low time revision 03 (may 26, 2009) connection diagrams corrected package name dual output read mode (dor) added statement for dual output read command quad output read mode (qor) added statement for quad output read command power up & power down updated v cc (low) min in table: power-up / power-down voltage and timing ac characteristics updated t wh , t ch and t wl , t cl revision history corrected ?revision 02 (february 12, 2009)? for ac characteristics revision 04 (july 22, 2009) distinctive characteristics added bga package information connection diagrams added bga package ordering information added automotive in-cabin information added bga package information valid combinations corrected valid combinations table configuration register added suggested cross settings table accelerated programming operation added note for acc function read identification (rdid) updated read identification description updated figure for rdid updated cfi table for 29h write registers (wrr) added note for hpm parameter sector erase (p4e, p8e) updated description for p4e/p8e command sector erase (se) updated description for se command
68 s25fl032p s25fl032p_00_09 january 29, 2013 data sheet release from deep power-down (res) added note for res command otp regions updated descriptions added esn1 and esn2 table operating ranges added automotive in-cabin temperature range ac characteristics added automotive in-cabin spec for f c updated t wh , t ch and t wl , t cl physical dimensions added bga 6 x 8 mm package revision 05 (october 5, 2009) global changed all references to rdid clock rate from 40 to 50 mhz connection diagrams added ?5 x 5 pin configuration? to figure 2.5 title added 6 x 4 pin configuration bga connection diagram added note regarding exposed central pad on bottom of package to the wson and uson connection diagram ordering information added automotive in-cabin temperature valid combinations for bga packages added 02 and 03 model numbers for bga packages removed bga from 00 model number description added low-halogen material option valid combinations changed valid bga model number combinations to 02 and 03 changed valid bga material option to low-halogen removed note 1 physical dimensions added fac024 bga package ac characteristics removed 76 mhz automotive in-cabin spec from f c and note 9 revision 06 (december 7, 2011) instruction set table updated qior command power-up / power-down voltage and timing table updated t pu (max) initial delivery state modified section capacitance added notes to table physical dimensions updated the package outline dr awing for soic, wson, uson, and bga 5x5 packages. revision 07 (september 21, 2012) ac characteristics changed output hold time (t ho ) to 2 ns (min) revision 08 (october 30, 2012) command definitions instruction set table: corrected the value of clsr command write registers (wrr) protection modes table: added parameter sector erase to memory content columns for clarification parameter sector erase (p4e, p8e) updated the table reference revision 09 (january 29, 2013) capacitance added ?typical? values column corrected ?max? values for c in / c out (input / output capacitance) section description
january 29, 2013 s25fl032p_00_09 s25fl032p 69 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any ot her warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2008-2013 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners.

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